net/phy/dp83822.c

25 #define DP83822_DEVADDR		0x1f
162 		phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1,
164 		phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2,
166 		phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3,
169 		value = phy_read_mmd(phydev, DP83822_DEVADDR,
177 			phy_write_mmd(phydev, DP83822_DEVADDR,
180 			phy_write_mmd(phydev, DP83822_DEVADDR,
183 			phy_write_mmd(phydev, DP83822_DEVADDR,
197 		return phy_write_mmd(phydev, DP83822_DEVADDR,
200 		return phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
229 	value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
235 		sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
240 		sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
245 		sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
435 		err = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
440 		err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
446 		err = phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
501 			err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
519 			ret = phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
522 			ret = phy_set_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
544 		ret = phy_set_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
553 		ret = phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
565 		ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83826_VOD_CFG1, mask, val);
573 		ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83826_VOD_CFG2, mask, val);
582 		ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83826_VOD_CFG2, mask, val);
673 	val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_SOR1);
738 	value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
752 	value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
754 	phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value |