ethernet/ti/am65-cpsw-qos.c

46 		writel(0, port->port_base + AM65_CPSW_PN_REG_PRI_CIR(prio));
47 		writel(0, port->port_base + AM65_CPSW_PN_REG_PRI_EIR(prio));
86 		       port->port_base + AM65_CPSW_PN_REG_PRI_CIR(prio));
98 		       port->port_base + AM65_CPSW_PN_REG_PRI_EIR(prio));
197 	writel(0, port->port_base + AM65_CPSW_PN_REG_TX_PRI_MAP);
259 	writel(tx_prio_map, port->port_base + AM65_CPSW_PN_REG_TX_PRI_MAP);
287 	writel(val, port->port_base + AM65_CPSW_PN_REG_IET_VERIFY);
302 		ctrl = readl(port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
304 		writel(ctrl, port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
307 		ctrl = readl(port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
309 		writel(ctrl, port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
313 		status = readl(port->port_base + AM65_CPSW_PN_REG_IET_STATUS);
342 	val = readl(port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
345 	writel(val, port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
360 		val = readl(port->port_base + AM65_CPSW_PN_REG_CTL);
390 	val = readl(port->port_base + AM65_CPSW_PN_REG_CTL);
404 	val = readl(port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
459 	val = readl(port->port_base + AM65_CPSW_PN_REG_CTL);
465 	writel(val, port->port_base + AM65_CPSW_PN_REG_CTL);
475 	val = readl(port->port_base + AM65_CPSW_PN_REG_EST_CTL);
481 	writel(val, port->port_base + AM65_CPSW_PN_REG_EST_CTL);
499 	val = readl(port->port_base + AM65_CPSW_PN_REG_FIFO_STATUS);
502 	val = readl(port->port_base + AM65_CPSW_PN_REG_EST_CTL);
558 	val = readl(port->port_base + AM65_CPSW_PN_REG_EST_CTL);
560 	writel(val, port->port_base + AM65_CPSW_PN_REG_EST_CTL);
1175 	writel(ch_cir, host->port_base + AM65_CPSW_PN_REG_PRI_CIR(tx_ch));
1264 		       host->port_base + AM65_CPSW_PN_REG_PRI_CIR(tx_ch));