Lines Matching defs:ioaddr
550 void __iomem *ioaddr;
599 static int eeprom_read(void __iomem *ioaddr, int location);
707 return np->ioaddr;
725 void __iomem *ioaddr = ns_ioaddr(dev);
742 writew(target, ioaddr + PhyCtrl);
743 readw(ioaddr + PhyCtrl);
810 void __iomem *ioaddr;
853 ioaddr = ioremap(iostart, iosize);
854 if (!ioaddr) {
860 prev_eedata = eeprom_read(ioaddr, 6);
862 int eedata = eeprom_read(ioaddr, i + 7);
870 np->ioaddr = ioaddr;
898 if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy)
946 np->srr = readl(ioaddr + SiliconRev);
977 iounmap(ioaddr);
1046 #define mii_delay(ioaddr) readl(ioaddr + EECtrl)
1051 void __iomem *ioaddr = ns_ioaddr(dev);
1053 writel(MII_ShiftClk, ioaddr + EECtrl);
1054 data = readl(ioaddr + EECtrl);
1055 writel(0, ioaddr + EECtrl);
1056 mii_delay(ioaddr);
1063 void __iomem *ioaddr = ns_ioaddr(dev);
1068 writel(mdio_val, ioaddr + EECtrl);
1069 mii_delay(ioaddr);
1070 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);
1071 mii_delay(ioaddr);
1073 writel(0, ioaddr + EECtrl);
1074 mii_delay(ioaddr);
1119 void __iomem *ioaddr = ns_ioaddr(dev);
1126 return readw(ioaddr+BasicControl+(reg<<2));
1134 void __iomem *ioaddr = ns_ioaddr(dev);
1138 writew(data, ioaddr+BasicControl+(reg<<2));
1146 void __iomem *ioaddr = ns_ioaddr(dev);
1178 readl(ioaddr + ChipConfig);
1200 cfg = readl(ioaddr + ChipConfig);
1218 writew(1, ioaddr + PGSEL);
1219 writew(PMDCSR_VAL, ioaddr + PMDCSR);
1220 writew(TSTDAT_VAL, ioaddr + TSTDAT);
1222 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG));
1223 writew(np->dspcfg, ioaddr + DSPCFG);
1224 writew(SDCFG_VAL, ioaddr + SDCFG);
1225 writew(0, ioaddr + PGSEL);
1226 readl(ioaddr + ChipConfig);
1229 writew(1, ioaddr + PGSEL);
1230 dspcfg = readw(ioaddr + DSPCFG);
1231 writew(0, ioaddr + PGSEL);
1252 readw(ioaddr + MIntrStatus);
1253 writew(MICRIntEn, ioaddr + MIntrCtrl);
1259 void __iomem *ioaddr = ns_ioaddr(dev);
1262 cfg = readl(ioaddr + ChipConfig);
1272 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);
1273 readl(ioaddr + ChipConfig);
1292 void __iomem *ioaddr = ns_ioaddr(dev);
1297 cfg = readl(ioaddr + ChipConfig);
1307 writel(cfg, ioaddr + ChipConfig);
1308 readl(ioaddr + ChipConfig);
1312 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1313 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
1314 readl(ioaddr + ChipConfig);
1317 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1393 void __iomem *ioaddr = ns_ioaddr(dev);
1404 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;
1406 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;
1408 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;
1411 writel(i*2, ioaddr + RxFilterAddr);
1412 pmatch[i] = readw(ioaddr + RxFilterData);
1416 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1417 sopass[i] = readw(ioaddr + RxFilterData);
1421 writel(ChipReset, ioaddr + ChipCmd);
1423 if (!(readl(ioaddr + ChipCmd) & ChipReset))
1436 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;
1442 writel(cfg, ioaddr + ChipConfig);
1444 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;
1445 writel(wcsr, ioaddr + WOLCmd);
1447 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;
1450 writel(i*2, ioaddr + RxFilterAddr);
1451 writew(pmatch[i], ioaddr + RxFilterData);
1454 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1455 writew(sopass[i], ioaddr + RxFilterData);
1458 writel(rfcr, ioaddr + RxFilterAddr);
1465 void __iomem *ioaddr = ns_ioaddr(dev);
1469 writel(RxReset, ioaddr + ChipCmd);
1472 np->intr_status |= readl(ioaddr + IntrStatus);
1489 void __iomem *ioaddr = ns_ioaddr(dev);
1492 writel(EepromReload, ioaddr + PCIBusCfg);
1495 if (!(readl(ioaddr + PCIBusCfg) & EepromReload))
1509 void __iomem * ioaddr = ns_ioaddr(dev);
1513 writel(RxOff | TxOff, ioaddr + ChipCmd);
1515 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1531 void __iomem * ioaddr = ns_ioaddr(dev);
1558 writel(i*2, ioaddr + RxFilterAddr);
1559 writew(mac, ioaddr + RxFilterData);
1561 writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
1568 dev->name, (int)readl(ioaddr + ChipCmd));
1581 void __iomem *ioaddr = ns_ioaddr(dev);
1595 if (readl(ioaddr + ChipConfig) & CfgSpeed100) {
1598 writew(1, ioaddr + PGSEL);
1603 data = readw(ioaddr + TSTDAT) & 0xff;
1612 writew(TSTDAT_FIXED, ioaddr + TSTDAT);
1614 data = readw(ioaddr + DSPCFG);
1616 writew(np->dspcfg, ioaddr + DSPCFG);
1618 writew(0, ioaddr + PGSEL);
1626 void __iomem * ioaddr = ns_ioaddr(dev);
1634 writew(1, ioaddr + PGSEL);
1636 data = readw(ioaddr + DSPCFG);
1638 writew(np->dspcfg, ioaddr + DSPCFG);
1639 writew(0, ioaddr + PGSEL);
1645 void __iomem * ioaddr = ns_ioaddr(dev);
1703 writel(np->tx_config, ioaddr + TxConfig);
1704 writel(np->rx_config, ioaddr + RxConfig);
1711 void __iomem * ioaddr = ns_ioaddr(dev);
1716 readl(ioaddr + IntrStatus);
1718 writel(np->ring_dma, ioaddr + RxRingPtr);
1720 ioaddr + TxRingPtr);
1738 writel(np->tx_config, ioaddr + TxConfig);
1748 writel(np->rx_config, ioaddr + RxConfig);
1756 np->SavedClkRun = readl(ioaddr + ClkRun);
1757 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
1760 dev->name, readl(ioaddr + WOLCmd));
1767 writel(DEFAULT_INTR, ioaddr + IntrMask);
1770 writel(RxOn | TxOn, ioaddr + ChipCmd);
1771 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
1791 void __iomem * ioaddr = ns_ioaddr(dev);
1808 writew(1, ioaddr+PGSEL);
1809 dspcfg = readw(ioaddr+DSPCFG);
1810 writew(0, ioaddr+PGSEL);
1846 writel(RxOn, ioaddr + ChipCmd);
1884 void __iomem * ioaddr = ns_ioaddr(dev);
1894 dev->name, readl(ioaddr + IntrStatus));
2089 void __iomem * ioaddr = ns_ioaddr(dev);
2125 writel(TxOn, ioaddr + ChipCmd);
2187 void __iomem * ioaddr = ns_ioaddr(dev);
2192 if (np->hands_off || !readl(ioaddr + IntrEnable))
2195 np->intr_status = readl(ioaddr + IntrStatus);
2204 readl(ioaddr + IntrMask));
2216 readl(ioaddr + IntrMask));
2228 void __iomem * ioaddr = ns_ioaddr(dev);
2236 readl(ioaddr + IntrMask));
2260 np->intr_status = readl(ioaddr + IntrStatus);
2284 void __iomem * ioaddr = ns_ioaddr(dev);
2323 writel(np->ring_dma, ioaddr + RxRingPtr);
2391 writel(RxOn, ioaddr + ChipCmd);
2397 void __iomem * ioaddr = ns_ioaddr(dev);
2411 readw(ioaddr + MIntrStatus);
2430 writel(np->tx_config, ioaddr + TxConfig);
2433 int wol_status = readl(ioaddr + WOLCmd);
2459 void __iomem * ioaddr = ns_ioaddr(dev);
2462 dev->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
2463 dev->stats.rx_missed_errors += readl(ioaddr + RxMissed);
2494 void __iomem * ioaddr = ns_ioaddr(dev);
2518 writel(HASH_TABLE + i, ioaddr + RxFilterAddr);
2520 ioaddr + RxFilterData);
2523 writel(rx_mode, ioaddr + RxFilterAddr);
2534 void __iomem * ioaddr = ns_ioaddr(dev);
2546 writel(np->ring_dma, ioaddr + RxRingPtr);
2548 writel(RxOn | TxOn, ioaddr + ChipCmd);
2705 void __iomem * ioaddr = ns_ioaddr(dev);
2706 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;
2727 writel(data, ioaddr + WOLCmd);
2735 void __iomem * ioaddr = ns_ioaddr(dev);
2736 u32 regval = readl(ioaddr + WOLCmd);
2771 void __iomem * ioaddr = ns_ioaddr(dev);
2780 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2782 writel(addr, ioaddr + RxFilterAddr);
2785 writel(addr | 0xa, ioaddr + RxFilterAddr);
2786 writew(sval[0], ioaddr + RxFilterData);
2788 writel(addr | 0xc, ioaddr + RxFilterAddr);
2789 writew(sval[1], ioaddr + RxFilterData);
2791 writel(addr | 0xe, ioaddr + RxFilterAddr);
2792 writew(sval[2], ioaddr + RxFilterData);
2795 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);
2803 void __iomem * ioaddr = ns_ioaddr(dev);
2813 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2815 writel(addr | 0xa, ioaddr + RxFilterAddr);
2816 sval[0] = readw(ioaddr + RxFilterData);
2818 writel(addr | 0xc, ioaddr + RxFilterAddr);
2819 sval[1] = readw(ioaddr + RxFilterData);
2821 writel(addr | 0xe, ioaddr + RxFilterAddr);
2822 sval[2] = readw(ioaddr + RxFilterData);
2824 writel(addr, ioaddr + RxFilterAddr);
3008 void __iomem * ioaddr = ns_ioaddr(dev);
3012 rbuf[i] = readl(ioaddr + i*4);
3020 writew(1, ioaddr + PGSEL);
3021 rbuf[i++] = readw(ioaddr + PMDCSR);
3022 rbuf[i++] = readw(ioaddr + TSTDAT);
3023 rbuf[i++] = readw(ioaddr + DSPCFG);
3024 rbuf[i++] = readw(ioaddr + SDCFG);
3025 writew(0, ioaddr + PGSEL);
3028 rfcr = readl(ioaddr + RxFilterAddr);
3030 writel(j*2, ioaddr + RxFilterAddr);
3031 rbuf[i++] = readw(ioaddr + RxFilterData);
3033 writel(rfcr, ioaddr + RxFilterAddr);
3058 void __iomem * ioaddr = ns_ioaddr(dev);
3063 ebuf[i] = eeprom_read(ioaddr, i);
3126 void __iomem * ioaddr = ns_ioaddr(dev);
3137 writel(0, ioaddr + RxRingPtr);
3140 readl(ioaddr + WOLCmd);
3143 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
3146 writel(RxOn, ioaddr + ChipCmd);
3152 writel(WOLPkt | LinkChange, ioaddr + IntrMask);
3159 void __iomem * ioaddr = ns_ioaddr(dev);
3166 dev->name, (int)readl(ioaddr + ChipCmd));
3198 readl(ioaddr + IntrMask);
3199 readw(ioaddr + MIntrStatus);
3202 writel(StatsFreeze, ioaddr + StatsCtrl);
3219 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3227 writel(np->SavedClkRun, ioaddr + ClkRun);
3237 void __iomem * ioaddr = ns_ioaddr(dev);
3241 iounmap(ioaddr);
3275 void __iomem * ioaddr = ns_ioaddr(dev);
3302 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3312 writel(np->SavedClkRun, ioaddr + ClkRun);