mlx5/core/en_dcbnl.c

107 				   struct ieee_ets *ets)
117 	if (!MLX5_CAP_GEN(priv->mdev, ets))
121 		err = mlx5_query_port_prio_tc(mdev, i, &ets->prio_tc[i]);
126 	ets->ets_cap = mlx5_max_tc(priv->mdev) + 1;
127 	for (i = 0; i < ets->ets_cap; i++) {
132 		err = mlx5_query_port_tc_bw_alloc(mdev, i, &ets->tc_tx_bw[i]);
136 		if (ets->tc_tx_bw[i] < MLX5E_MAX_BW_ALLOC &&
144 	/* Report 0% ets tc if exits*/
146 		for (i = 0; i < ets->ets_cap; i++)
148 				ets->tc_tx_bw[i] = 0;
152 	for (i = 0; i < ets->ets_cap; i++) {
153 		if (ets->tc_tx_bw[i] < MLX5E_MAX_BW_ALLOC)
159 	memcpy(ets->tc_tsa, priv->dcbx.tc_tsa, sizeof(ets->tc_tsa));
164 static void mlx5e_build_tc_group(struct ieee_ets *ets, u8 *tc_group, int max_tc)
172 		if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS) {
174 			if (!ets->tc_tx_bw[i])
179 	/* strict group has higher priority than ets group */
187 		switch (ets->tc_tsa[i]) {
196 			if (ets->tc_tx_bw[i] && ets_zero_bw)
203 static void mlx5e_build_tc_tx_bw(struct ieee_ets *ets, u8 *tc_tx_bw,
212 		if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS &&
213 		    !ets->tc_tx_bw[i]) {
223 		switch (ets->tc_tsa[i]) {
231 			tc_tx_bw[i] = ets->tc_tx_bw[i] ?
232 				      ets->tc_tx_bw[i] :
238 	/* Make sure the total bw for ets zero bw group is 100% */
251 static int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets)
259 	mlx5e_build_tc_group(ets, tc_group, max_tc);
260 	mlx5e_build_tc_tx_bw(ets, tc_tx_bw, tc_group, max_tc);
262 	err = mlx5_set_port_prio_tc(mdev, ets->prio_tc);
275 	memcpy(priv->dcbx.tc_tsa, ets->tc_tsa, sizeof(ets->tc_tsa));
279 			   __func__, i, ets->prio_tc[i]);
288 				    struct ieee_ets *ets,
297 		if (ets->prio_tc[i] >= MLX5E_MAX_PRIORITY) {
307 		if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS) {
309 			bw_sum += ets->tc_tx_bw[i];
323 				   struct ieee_ets *ets)
328 	if (!MLX5_CAP_GEN(priv->mdev, ets))
331 	err = mlx5e_dbcnl_validate_ets(netdev, ets, false);
335 	err = mlx5e_dcbnl_ieee_setets_core(priv, ets);
626 	struct ieee_ets ets;
631 	if (!MLX5_CAP_GEN(mdev, ets))
634 	memset(&ets, 0, sizeof(ets));
637 	ets.ets_cap = IEEE_8021QAZ_MAX_TCS;
639 		ets.tc_tx_bw[i] = cee_cfg->pg_bw_pct[i];
640 		ets.tc_rx_bw[i] = cee_cfg->pg_bw_pct[i];
641 		ets.tc_tsa[i]   = IEEE_8021QAZ_TSA_ETS;
642 		ets.prio_tc[i]  = cee_cfg->prio_to_pg_map[i];
645 			   __func__, i, ets.tc_tx_bw[i], ets.tc_rx_bw[i],
646 			   ets.prio_tc[i]);
649 	err = mlx5e_dbcnl_validate_ets(netdev, &ets, true);
653 	err = mlx5e_dcbnl_ieee_setets_core(priv, &ets);
740 	if (!MLX5_CAP_GEN(priv->mdev, ets)) {
741 		netdev_err(netdev, "%s, ets is not supported\n", __func__);
762 	struct ieee_ets ets;
770 	mlx5e_dcbnl_ieee_getets(netdev, &ets);
771 	*bw_pct = ets.tc_tx_bw[pgid];
1051 	struct ieee_ets ets;
1055 	if (!MLX5_CAP_GEN(priv->mdev, ets))
1058 	memset(&ets, 0, sizeof(ets));
1059 	ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
1060 	for (i = 0; i < ets.ets_cap; i++) {
1061 		ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
1062 		ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
1063 		ets.prio_tc[i] = i;
1066 	if (ets.ets_cap > 1) {
1068 		ets.prio_tc[0] = 1;
1069 		ets.prio_tc[1] = 0;
1072 	err = mlx5e_dcbnl_ieee_setets_core(priv, &ets);