hisilicon/hns3/hns3_enet.c

658 static void hns3_tqp_enable(struct hnae3_queue *tqp)
662 	rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
664 	hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
667 static void hns3_tqp_disable(struct hnae3_queue *tqp)
671 	rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
673 	hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
729 		hns3_tqp_enable(h->kinfo.tqp[j]);
736 			hns3_tqp_disable(h->kinfo.tqp[j]);
758 						  ring->tqp->tqp_index);
836 		hns3_tqp_disable(h->kinfo.tqp[i]);
1034 	u32 alloc_size = ring->tqp->handle->kinfo.tx_spare_buf_size;
1083 	ring->tqp->handle->kinfo.tx_spare_buf_size = 0;
1487 	struct hnae3_handle *handle = tx_ring->tqp->handle;
2068 	__iowrite64_copy(ring->tqp->mem_base, desc,
2086 	__iowrite64_copy(ring->tqp->mem_base + HNS3_MEM_DOORBELL_OFFSET,
2127 	if (ring->tqp->mem_base)
2131 		       ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
3651 	dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
3702 				writel(i, ring->tqp->io_base +
3714 	writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
3972 	struct hnae3_handle *handle = ring->tqp->handle;
3973 	struct pci_dev *pdev = ring->tqp->handle->pdev;
4393 	skb_record_rx_queue(skb, ring->tqp->tqp_index);
4545 		chain->tqp_index = ring->tqp->tqp_index;
4894 	ring->tqp = q;
4905 static void hns3_queue_to_ring(struct hnae3_queue *tqp,
4908 	hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
4909 	hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
4926 		hns3_queue_to_ring(h->kinfo.tqp[i], priv);
5058 	struct hnae3_queue *q = ring->tqp;
5092 			q = priv->ring[tc_info->tqp_offset[i] + j].tqp;
5782 			"Change tqp num(%u) fail.\n", new_tqp_num);
5822 			"Change tqps fail, the tqp range is from 1 to %u",
5881 		hns3_tqp_disable(h->kinfo.tqp[i]);
5917 		hns3_tqp_enable(h->kinfo.tqp[i]);