chelsio/cxgb4/t4_hw.c

61 		u32 val = t4_read_reg(adapter, reg);
95 	u32 v = t4_read_reg(adapter, addr) & ~mask;
98 	(void) t4_read_reg(adapter, addr);      /* flush */
119 		*vals++ = t4_read_reg(adap, data_reg);
165 	*val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
197 	pcie_fw = t4_read_reg(adap, PCIE_FW_A);
335 		pcie_fw = t4_read_reg(adap, PCIE_FW_A);
366 	v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
368 		v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
384 	t4_read_reg(adap, ctl_reg);          /* flush write */
390 	     !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
401 		v = t4_read_reg(adap, ctl_reg);
469 		t4_read_reg(adap, edc_ecc_err_addr_reg));
509 	edc_size  = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
515 		mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
528 	mem_reg = t4_read_reg(adap,
559 	t4_read_reg(adap,
585 					t4_read_reg(adap, addr));
693 			*buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
818 	t4_read_reg(adap,
2683 			*bufp++ = t4_read_reg(adap, reg);
2934 	if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2940 		*valp = t4_read_reg(adapter, SF_DATA_A);
2961 	if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
3873 	cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3877 	val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3889 			*pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3890 			*pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3905 	cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3914 			*ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3915 			*ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3929 		j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3932 			*p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
4291 	unsigned int status = t4_read_reg(adapter, reg);
4487 	perr = t4_read_reg(adapter, SGE_INT_CAUSE1_A);
4494 	perr = t4_read_reg(adapter, SGE_INT_CAUSE2_A);
4502 		perr = t4_read_reg(adapter, SGE_INT_CAUSE5_A);
4517 	err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4588 	fw_err = t4_read_reg(adapter, PCIE_FW_A);
4599 	val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
4824 	t4_read_reg(adapter, MPS_INT_CAUSE_A);                    /* flush */
4857 	v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4862 		u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4886 	u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4891 			  t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4895 				  t4_read_reg(adap,
4899 		v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4954 	v = t4_read_reg(adap, int_cause_reg);
5004 	u32 raw_cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
5005 	u32 enable = t4_read_reg(adapter, PL_INT_ENABLE_A);
5059 	(void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
5079 	u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5111 	whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5473 	u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
5538 	vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
5746 		v = t4_read_reg(adap, TP_MTU_TABLE_A);
5769 			incr[mtu][w] = (u16)t4_read_reg(adap,
5787 	val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5911 	v = t4_read_reg(adap, TP_TX_TRATE_A);
5919 	v = t4_read_reg(adap, TP_TX_ORATE_A);
5950 	cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
6012 	ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
6013 	ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
6034 		tp->mask[i] = ~t4_read_reg(adap, mask_reg);
6035 		tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
6054 		cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
6081 		cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
6108 	nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6147 	nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6210 	nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6242 	unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
6347 	u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
6755 			sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6871 		if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6921 			pcie_fw = t4_read_reg(adap, PCIE_FW_A);
7123 			if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
7223 	sge_control = t4_read_reg(adap, SGE_CONTROL_A);
7249 		sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
7401 		     (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
7404 		     (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
9120 	pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
9219 			     t4_read_reg(adapter, a_port_cfg)
9337 		t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
9385 	hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
9394 	qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
9396 	qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
9415 	v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
9471 		v = t4_read_reg(adap, TP_OUT_CONFIG_A);
9501 	v = t4_read_reg(adap, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A);
9503 	v = t4_read_reg(adap, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A);
9752 		v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9761 		v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9804 		*data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
9833 	v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9847 		*data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
9867 	if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9875 			*valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
9894 	if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9996 	cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
10001 	val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
10086 	idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
10087 	idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10139 		debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10143 		debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10268 		v = t4_read_reg(adap, TP_PACE_TABLE_A);
10370 			*data++ = t4_read_reg(adap, i);