Lines Matching refs:adap
103 * @adap: the adapter
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
118 t4_write_reg(adap, addr_reg, start_idx);
119 *vals++ = t4_read_reg(adap, data_reg);
126 * @adap: the adapter
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
161 if (is_t4(adap->params.chip))
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
177 * @adap: the adapter
183 static void t4_report_fw_error(struct adapter *adap)
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
201 adap->flags &= ~CXGB4_FW_OK;
208 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
212 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
218 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
222 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
223 dev_alert(adap->pdev_dev,
261 * @adap: the adapter
282 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
308 if (adap->pdev->error_state != pci_channel_io_normal)
322 spin_lock_bh(&adap->mbox_lock);
323 list_add_tail(&entry.list, &adap->mlist.list);
324 spin_unlock_bh(&adap->mbox_lock);
335 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
337 spin_lock_bh(&adap->mbox_lock);
339 spin_unlock_bh(&adap->mbox_lock);
341 t4_record_mbox(adap, cmd, size, access, ret);
348 if (list_first_entry(&adap->mlist.list, struct mbox_list,
366 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
368 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
370 spin_lock_bh(&adap->mbox_lock);
372 spin_unlock_bh(&adap->mbox_lock);
374 t4_record_mbox(adap, cmd, size, access, ret);
379 t4_record_mbox(adap, cmd, size, access, 0);
381 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
383 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
384 t4_read_reg(adap, ctl_reg); /* flush write */
390 !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
401 v = t4_read_reg(adap, ctl_reg);
404 t4_write_reg(adap, ctl_reg, 0);
408 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
412 fw_asrt(adap, data_reg);
418 t4_write_reg(adap, ctl_reg, 0);
421 t4_record_mbox(adap, cmd_rpl,
423 spin_lock_bh(&adap->mbox_lock);
425 spin_unlock_bh(&adap->mbox_lock);
431 t4_record_mbox(adap, cmd, size, access, ret);
432 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
434 t4_report_fw_error(adap);
435 spin_lock_bh(&adap->mbox_lock);
437 spin_unlock_bh(&adap->mbox_lock);
438 t4_fatal_err(adap);
442 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
445 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
449 static int t4_edc_err_read(struct adapter *adap, int idx)
454 if (is_t4(adap->params.chip)) {
455 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
459 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
466 CH_WARN(adap,
469 t4_read_reg(adap, edc_ecc_err_addr_reg));
470 CH_WARN(adap,
473 (unsigned long long)t4_read_reg64(adap, rdata_reg),
474 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
475 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
476 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
477 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
478 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
479 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
480 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
481 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
488 * @adap: the adapter
497 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
509 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
515 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
528 mem_reg = t4_read_reg(adap,
537 if (is_t4(adap->params.chip))
538 *mem_base -= adap->t4_bar0;
545 * @adap: the adapter
551 void t4_memory_update_win(struct adapter *adap, int win, u32 addr)
553 t4_write_reg(adap,
559 t4_read_reg(adap,
565 * @adap: the adapter
573 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
585 t4_read_reg(adap, addr));
592 t4_write_reg(adap, addr,
599 * @adap: the adapter
614 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
636 ret = t4_memory_rw_init(adap, win, mtype, &memoffset, &mem_base,
644 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
655 t4_memory_update_win(adap, win, pos | win_pf);
693 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
696 t4_write_reg(adap, mem_base + offset,
710 t4_memory_update_win(adap, win, pos | win_pf);
720 t4_memory_rw_residual(adap, resid, mem_base + offset,
731 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
750 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
756 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
764 t4_hw_pci_read_cfg4(adap, reg, &val);
772 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
777 if (is_t4(adap->params.chip)) {
789 bar0 = t4_read_pcie_cfg4(adap, pci_base);
791 adap->t4_bar0 = bar0;
802 u32 t4_get_util_window(struct adapter *adap)
804 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
812 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
814 t4_write_reg(adap,
818 t4_read_reg(adap,
848 * @adap: the adapter
856 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
2643 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2665 dev_err(adap->pdev_dev,
2683 *bufp++ = t4_read_reg(adap, reg);
3145 * @adap: the adapter
3153 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3163 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3355 * @adap: the adapter
3361 int t4_check_fw_version(struct adapter *adap)
3365 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3367 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3370 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3375 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3376 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3377 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3396 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3397 adap->chip);
3403 dev_err(adap->pdev_dev,
3435 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3453 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3463 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3475 ret = t4_read_flash(adap, FLASH_FW_START,
3481 dev_err(adap->pdev_dev,
3501 should_install_fs_fw(adap, card_fw_usable,
3504 ret = t4_fw_upgrade(adap, adap->mbox, fw_data,
3507 dev_err(adap->pdev_dev,
3525 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3541 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3542 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3599 static bool t4_fw_matches_chip(const struct adapter *adap,
3605 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3606 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3607 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3610 dev_err(adap->pdev_dev,
3612 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3618 * @adap: the adapter
3624 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3632 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3638 dev_err(adap->pdev_dev, "FW image has no data\n");
3642 dev_err(adap->pdev_dev,
3647 dev_err(adap->pdev_dev,
3652 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3656 if (!t4_fw_matches_chip(adap, hdr))
3663 dev_err(adap->pdev_dev,
3669 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3680 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, true);
3688 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, true);
3693 ret = t4_write_flash(adap, fw_start + offsetof(struct fw_hdr, fw_ver),
3698 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3701 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3707 * @adap: the adapter
3713 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3720 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3722 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3732 * @adap: the adapter
3754 int t4_load_phy_fw(struct adapter *adap, int win,
3768 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3773 CH_WARN(adap, "PHY Firmware already up-to-date, "
3787 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3790 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3800 spin_lock_bh(&adap->win0_lock);
3801 ret = t4_memory_rw(adap, win, mtype, maddr,
3804 spin_unlock_bh(&adap->win0_lock);
3815 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3817 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3826 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3831 CH_WARN(adap, "PHY Firmware did not update: "
3844 * @adap: the adapter
3847 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3855 FW_PARAMS_CMD_PFN_V(adap->pf) |
3863 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3866 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3873 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3875 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3877 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3887 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3889 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3890 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3897 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3900 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3905 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3907 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3912 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3914 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3915 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3918 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3921 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3928 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3929 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3930 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3932 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
4236 * @adap: the adapter
4242 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4244 unsigned int fw_caps = adap->params.fw_caps_support;
4260 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4263 typedef void (*int_handler_t)(struct adapter *adap);
4716 static void le_intr_handler(struct adapter *adap)
4718 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4739 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4742 t4_fatal_err(adap);
4884 static void ma_intr_handler(struct adapter *adap)
4886 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4889 dev_alert(adap->pdev_dev,
4891 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4892 if (is_t5(adap->params.chip))
4893 dev_alert(adap->pdev_dev,
4895 t4_read_reg(adap,
4899 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4900 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4905 t4_write_reg(adap, MA_INT_CAUSE_A, status);
4906 t4_fatal_err(adap);
4912 static void smb_intr_handler(struct adapter *adap)
4921 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4922 t4_fatal_err(adap);
4928 static void ncsi_intr_handler(struct adapter *adap)
4938 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4939 t4_fatal_err(adap);
4945 static void xgmac_intr_handler(struct adapter *adap, int port)
4949 if (is_t4(adap->params.chip))
4954 v = t4_read_reg(adap, int_cause_reg);
4961 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4964 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4966 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4967 t4_fatal_err(adap);
4973 static void pl_intr_handler(struct adapter *adap)
4981 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4982 t4_fatal_err(adap);
5119 unsigned int t4_chip_rss_size(struct adapter *adap)
5121 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
5249 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5251 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
5252 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
5279 static unsigned int t4_use_ldst(struct adapter *adap)
5281 return (adap->flags & CXGB4_FW_OK) && !adap->use_bd;
5286 * @adap: the adapter
5296 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
5315 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
5328 * @adap: the adapter
5340 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
5361 if (t4_use_ldst(adap))
5362 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
5369 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
5372 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
5379 * @adap: the adapter
5387 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5390 t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5396 * @adap: the adapter
5404 static void t4_tp_pio_write(struct adapter *adap, u32 *buff, u32 nregs,
5407 t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5413 * @adap: the adapter
5421 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5424 t4_tp_indirect_rw(adap, TP_TM_PIO_ADDR_A, TP_TM_PIO_DATA_A, buff,
5430 * @adap: the adapter
5438 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5441 t4_tp_indirect_rw(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, buff, nregs,
5447 * @adap: the adapter
5453 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5455 t4_tp_pio_read(adap, key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5460 * @adap: the adapter
5469 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5473 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
5479 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
5483 t4_tp_pio_write(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5487 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5491 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5581 * @adap: the adapter
5589 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5599 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5607 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5621 * @adap: the adapter
5627 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
5630 int nchan = adap->params.arch.nchan;
5632 t4_tp_mib_read(adap, st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A,
5634 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A,
5636 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A,
5638 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
5640 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
5642 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A,
5644 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
5646 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
5648 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A,
5654 * @adap: the adapter
5660 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
5663 int nchan = adap->params.arch.nchan;
5665 t4_tp_mib_read(adap, st->req, nchan, TP_MIB_CPL_IN_REQ_0_A, sleep_ok);
5667 t4_tp_mib_read(adap, st->rsp, nchan, TP_MIB_CPL_OUT_RSP_0_A, sleep_ok);
5672 * @adap: the adapter
5678 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
5681 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, TP_MIB_RQE_DFR_PKT_A,
5687 * @adap: the adapter
5694 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5699 t4_tp_mib_read(adap, &st->frames_ddp, 1, TP_MIB_FCOE_DDP_0_A + idx,
5702 t4_tp_mib_read(adap, &st->frames_drop, 1,
5705 t4_tp_mib_read(adap, val, 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx,
5713 * @adap: the adapter
5719 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
5724 t4_tp_mib_read(adap, val, 4, TP_MIB_USM_PKTS_A, sleep_ok);
5732 * @adap: the adapter
5738 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5744 t4_write_reg(adap, TP_MTU_TABLE_A,
5746 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5755 * @adap: the adapter
5761 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5767 t4_write_reg(adap, TP_CCTRL_TABLE_A,
5769 incr[mtu][w] = (u16)t4_read_reg(adap,
5776 * @adap: the adapter
5783 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5786 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5787 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5788 t4_write_reg(adap, TP_PIO_DATA_A, val);
5840 * @adap: the adapter
5850 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5867 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5876 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5891 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5893 u64 v = bytes256 * adap->params.vpd.cclk;
5900 * @adap: the adapter
5907 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5911 v = t4_read_reg(adap, TP_TX_TRATE_A);
5912 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5913 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5914 if (adap->params.arch.nchan == NCHAN) {
5915 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5916 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5919 v = t4_read_reg(adap, TP_TX_ORATE_A);
5920 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5921 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5922 if (adap->params.arch.nchan == NCHAN) {
5923 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5924 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5930 * @adap: the adapter
5939 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5946 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5950 cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5967 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5973 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5980 t4_write_reg(adap, data_reg, tp->data[i]);
5981 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5983 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5986 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5988 (is_t4(adap->params.chip) ?
5998 * @adap: the adapter
6005 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
6012 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
6013 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
6015 if (is_t4(adap->params.chip)) {
6034 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
6035 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
6041 * @adap: the adapter
6047 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6052 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
6053 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
6054 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
6055 if (is_t4(adap->params.chip)) {
6056 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
6058 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
6068 * @adap: the adapter
6074 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6079 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
6080 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
6081 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
6082 if (is_t4(adap->params.chip)) {
6083 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
6085 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
6232 * @adap: the adapter
6239 unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
6241 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
6242 unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
6245 dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n",
6272 dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n",
6317 * @adap: The adapter
6322 void t4_get_port_stats_offset(struct adapter *adap, int idx,
6329 t4_get_port_stats(adap, idx, stats);
6338 * @adap: the adapter
6344 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
6346 u32 bgmap = t4_get_mps_bg_map(adap, idx);
6347 u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
6350 t4_read_reg64(adap, \
6351 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
6353 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6379 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6413 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6435 * @adap: the adapter
6441 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6443 u32 bgmap = t4_get_mps_bg_map(adap, idx);
6446 t4_read_reg64(adap, \
6447 (is_t4(adap->params.chip) ? \
6450 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6509 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
6525 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6530 * @adap: the adapter
6539 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6556 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6564 * @adap: the adapter
6573 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6590 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6760 * @adap: the adapter
6767 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type)
6783 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6789 * @adap: the adapter
6797 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers,
6817 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
6830 * @adap: the adapter
6839 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6867 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6871 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6872 t4_report_fw_error(adap);
6921 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6960 * @adap: the adapter
6965 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6971 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6976 * @adap: the adapter
6982 int t4_early_init(struct adapter *adap, unsigned int mbox)
6988 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6993 * @adap: the adapter
6999 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
7006 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7011 * @adap: the adapter
7025 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
7040 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7057 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
7058 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
7071 * @adap: the adapter
7091 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
7099 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
7109 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
7111 if (t4_fw_reset(adap, mbox,
7116 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
7121 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
7123 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
7135 * @adap: the adapter
7154 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
7160 if (!t4_fw_matches_chip(adap, fw_hdr))
7166 adap->flags &= ~CXGB4_FW_OK;
7168 ret = t4_fw_halt(adap, mbox, force);
7172 ret = t4_load_fw(adap, fw_data, size);
7185 (void)t4_load_cfg(adap, NULL, 0);
7196 ret = t4_fw_restart(adap, mbox, reset);
7203 (void)t4_init_devlog_params(adap);
7205 adap->flags |= CXGB4_FW_OK;
7211 * @adap: the adapter
7218 int t4_fl_pkt_align(struct adapter *adap)
7223 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
7237 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
7245 if (!is_t4(adap->params.chip)) {
7249 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
7264 * @adap: the adapter
7272 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
7281 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
7291 if (is_t4(adap->params.chip)) {
7292 t4_set_reg_field(adap, SGE_CONTROL_A,
7325 if (pci_is_pcie(adap->pdev)) {
7333 pcie_capability_read_word(adap->pdev, PCI_EXP_DEVCTL,
7364 if (is_t5(adap->params.chip))
7369 t4_set_reg_field(adap, SGE_CONTROL_A,
7374 t4_set_reg_field(adap, SGE_CONTROL2_A,
7399 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
7400 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
7401 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
7403 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
7404 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
7407 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
7414 * @adap: the adapter
7420 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7426 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7431 * @adap: the adapter
7444 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7469 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7476 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7480 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7484 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
7488 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7494 * @adap: the adapter
7506 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7529 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7534 * @adap: the adapter
7545 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7549 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7555 * @adap: the adapter
7574 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7598 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7603 * @adap: the adapter
7620 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7635 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7669 * @adap: the adapter
7677 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7691 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7696 * @adap: the adapter
7709 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7748 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7753 ret = t4_wr_mbox_meat(adap, mbox, &c_mirror, sizeof(c_mirror),
7761 * @adap: the adapter
7770 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
7791 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7797 * @adap: the adapter
7810 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
7842 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7847 * @adap: the adapter
7861 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
7888 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7896 * @adap: the adapter
7909 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
7940 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7952 * @adap: the adapter
7972 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
7979 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
8016 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8046 * @adap: the adapter
8057 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
8064 unsigned int max_naddr = is_t4(adap->params.chip) ?
8098 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8121 * @adap: the adapter
8138 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
8144 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
8160 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
8166 if (adap->params.viid_smt_extn_support) {
8175 if (CHELSIO_CHIP_VERSION(adap->params.chip) <=
8188 * @adap: the adapter
8197 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
8210 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
8215 * @adap: the adapter
8225 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
8238 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
8243 * @adap: the adapter
8251 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
8254 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
8259 * @adap: the adapter
8272 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
8276 int ret = t4_enable_vi_params(adap, mbox, pi->viid,
8280 t4_os_link_changed(adap, pi->port_id,
8287 * @adap: the adapter
8294 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
8305 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8310 * @adap: the adapter
8323 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
8338 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8343 * @adap: the adapter
8354 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8369 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8374 * @adap: the adapter
8382 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8394 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8399 * @adap: the adapter
8407 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8419 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8424 * @adap: the adapter
8432 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8444 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8838 * @adap: the adapter
8843 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8863 for_each_port(adap, i) {
8864 pi = adap2pinfo(adap, i);
8871 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n",
8952 static int t4_get_flash_params(struct adapter *adap)
8972 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
8974 ret = sf1_read(adap, 3, 0, 1, &flashid);
8975 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
8983 adap->params.sf_size = supported_flash[part].size_mb;
8984 adap->params.sf_nsec =
8985 adap->params.sf_size / SF_SEC_SIZE;
9089 dev_warn(adap->pdev_dev, "Unknown Flash Part, ID = %#x, assuming 4MB\n",
9095 adap->params.sf_size = size;
9096 adap->params.sf_nsec = size / SF_SEC_SIZE;
9099 if (adap->params.sf_size < FLASH_MIN_SIZE)
9100 dev_warn(adap->pdev_dev, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
9101 flashid, adap->params.sf_size, FLASH_MIN_SIZE);
9319 * @adap: the adapter
9324 int t4_init_devlog_params(struct adapter *adap)
9326 struct devlog_params *dparams = &adap->params.devlog;
9337 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
9357 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
9372 * t4_init_sge_params - initialize adap->params.sge
9403 * t4_init_tp_params - initialize adap->params.tp
9404 * @adap: the adapter
9409 int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
9415 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
9416 adap->params.tp.tre = TIMERRESOLUTION_G(v);
9417 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
9421 adap->params.tp.tx_modq[chan] = chan;
9431 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
9434 dev_info(adap->pdev_dev,
9438 adap->params.tp.vlan_pri_map =
9440 adap->params.tp.filter_mask =
9443 dev_info(adap->pdev_dev,
9451 t4_tp_pio_read(adap, &adap->params.tp.vlan_pri_map, 1,
9461 adap->params.tp.filter_mask = adap->params.tp.vlan_pri_map;
9464 t4_tp_pio_read(adap, &adap->params.tp.ingress_config, 1,
9470 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
9471 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
9472 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
9479 adap->params.tp.fcoe_shift = t4_filter_field_shift(adap, FCOE_F);
9480 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
9481 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
9482 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
9483 adap->params.tp.tos_shift = t4_filter_field_shift(adap, TOS_F);
9484 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
9486 adap->params.tp.ethertype_shift = t4_filter_field_shift(adap,
9488 adap->params.tp.macmatch_shift = t4_filter_field_shift(adap,
9490 adap->params.tp.matchtype_shift = t4_filter_field_shift(adap,
9492 adap->params.tp.frag_shift = t4_filter_field_shift(adap,
9498 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
9499 adap->params.tp.vnic_shift = -1;
9501 v = t4_read_reg(adap, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A);
9502 adap->params.tp.hash_filter_mask = v;
9503 v = t4_read_reg(adap, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A);
9504 adap->params.tp.hash_filter_mask |= ((u64)v << 32);
9510 * @adap: the adapter
9517 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
9519 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
9563 int t4_init_rss_mode(struct adapter *adap, int mbox)
9570 for_each_port(adap, i) {
9571 struct port_info *p = adap2pinfo(adap, i);
9578 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
9696 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
9701 for_each_port(adap, i) {
9702 struct port_info *pi = adap2pinfo(adap, i);
9704 while ((adap->params.portvec & (1 << j)) == 0)
9711 eth_hw_addr_set(adap->port[i], addr);
9735 * @adap: the adapter
9743 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
9746 int cim_num_obq = is_t4(adap->params.chip) ?
9750 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
9752 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9759 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9761 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9770 * @adap: the adapter
9779 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9798 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
9800 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
9804 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
9806 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
9812 * @adap: the adapter
9821 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9825 int cim_num_obq = is_t4(adap->params.chip) ?
9831 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9833 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9841 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
9843 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
9847 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
9849 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
9855 * @adap: the adapter
9862 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
9867 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9871 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
9872 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9875 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
9882 * @adap: the adapter
9889 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
9894 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9898 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
9899 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
9900 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9906 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
9909 return t4_cim_write(adap, addr, 1, &val);
9914 * @adap: the adapter
9922 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
9927 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
9932 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
9937 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9945 for (i = 0; i < adap->params.cim_la_size; i++) {
9946 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9950 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9957 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
9964 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
9973 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9983 * @adap: the adapter
9991 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
9996 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
9998 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9999 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
10001 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
10011 val |= adap->params.tp.la_mask;
10014 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
10015 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
10024 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
10025 cfg | adap->params.tp.la_mask);
10157 * @adap: the adapter
10163 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
10168 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10170 cfg_addr = t4_flash_cfg_addr(adap);
10178 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
10185 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10199 ret = t4_write_flash(adap, addr, n, cfg_data, true);
10209 dev_err(adap->pdev_dev, "config file %s failed %d\n",
10257 * @adap: the adapter
10262 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
10267 t4_write_reg(adap, TP_PACE_TABLE_A, 0xffff0000 + i);
10268 v = t4_read_reg(adap, TP_PACE_TABLE_A);
10269 pace_vals[i] = dack_ticks_to_usec(adap, v);
10275 * @adap: the adapter
10283 void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
10290 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10298 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
10304 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10308 *ipg = (10000 * v) / core_ticks_per_usec(adap);
10313 * @adap: the adapter
10321 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
10339 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
10353 * @adap: the adapter
10361 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
10366 t4_write_reg(adap, SGE_CTXT_CMD_A, CTXTQID_V(cid) | CTXTTYPE_V(ctype));
10367 ret = t4_wait_op_done(adap, SGE_CTXT_CMD_A, BUSY_F, 0, 3, 1);
10370 *data++ = t4_read_reg(adap, i);
10407 * @adap: the adapter
10417 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
10448 ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd),
10464 * @adap: the adapter
10469 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
10481 FW_ACL_VLAN_CMD_PFN_V(adap->pf) |
10493 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL);
10567 * @adap: the adapter
10576 int t4_load_boot(struct adapter *adap, u8 *boot_data,
10579 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10592 dev_err(adap->pdev_dev, "boot image encroaching on firmware region\n");
10608 dev_err(adap->pdev_dev, "boot image too small/large\n");
10613 dev_err(adap->pdev_dev, "Boot image missing signature\n");
10619 dev_err(adap->pdev_dev, "PCI header missing signature\n");
10625 dev_err(adap->pdev_dev, "Vendor ID missing signature\n");
10635 ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
10645 pci_read_config_word(adap->pdev, PCI_DEVICE_ID, &device_id);
10668 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data,
10674 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE,
10679 dev_err(adap->pdev_dev, "boot image load failed, error %d\n",
10706 int t4_load_bootcfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
10708 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10714 cfg_addr = t4_flash_bootcfg_addr(adap);
10722 dev_err(adap->pdev_dev, "bootcfg file too large, max is %u bytes\n",
10729 dev_err(adap->pdev_dev, "Wrong bootcfg signature\n");
10736 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10750 ret = t4_write_flash(adap, addr, n, cfg_data, false);
10762 ret = t4_write_flash(adap, cfg_addr + size + i, 1, &data,
10770 dev_err(adap->pdev_dev, "boot config data %s failed %d\n",