cavium/common/cavium_ptp.c

2 /* cavium_ptp.c - PTP 1588 clock on Cavium hardware
89  * @ptp_info: PTP clock info
95 	struct cavium_ptp *clock =
107 	/* The hardware adds the clock compensation value to the PTP clock
108 	 * on every coprocessor clock cycle. Typical convention is that it
122 	comp = ((u64)1000000000ull << 32) / clock->clock_rate;
128 	spin_lock_irqsave(&clock->spin_lock, flags);
129 	writeq(comp, clock->reg_base + PTP_CLOCK_COMP);
130 	spin_unlock_irqrestore(&clock->spin_lock, flags);
137  * @ptp_info:   PTP clock info
142 	struct cavium_ptp *clock =
146 	spin_lock_irqsave(&clock->spin_lock, flags);
147 	timecounter_adjtime(&clock->time_counter, delta);
148 	spin_unlock_irqrestore(&clock->spin_lock, flags);
157  * cavium_ptp_gettime() - Get hardware clock time with adjustment
158  * @ptp_info: PTP clock info
164 	struct cavium_ptp *clock =
169 	spin_lock_irqsave(&clock->spin_lock, flags);
170 	nsec = timecounter_read(&clock->time_counter);
171 	spin_unlock_irqrestore(&clock->spin_lock, flags);
179  * cavium_ptp_settime() - Set hardware clock time. Reset adjustment
180  * @ptp_info: PTP clock info
186 	struct cavium_ptp *clock =
193 	spin_lock_irqsave(&clock->spin_lock, flags);
194 	timecounter_init(&clock->time_counter, &clock->cycle_counter, nsec);
195 	spin_unlock_irqrestore(&clock->spin_lock, flags);
202  * @ptp_info: PTP clock info
214 	struct cavium_ptp *clock =
217 	return readq(clock->reg_base + PTP_CLOCK_HI);
224 	struct cavium_ptp *clock;
230 	clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL);
231 	if (!clock) {
236 	clock->pdev = pdev;
246 	clock->reg_base = pcim_iomap_table(pdev)[PCI_PTP_BAR_NO];
248 	spin_lock_init(&clock->spin_lock);
250 	cc = &clock->cycle_counter;
256 	timecounter_init(&clock->time_counter, &clock->cycle_counter,
259 	clock->clock_rate = ptp_cavium_clock_get();
261 	clock->ptp_info = (struct ptp_clock_info) {
275 	clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG);
277 	writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG);
279 	clock_comp = ((u64)1000000000ull << 32) / clock->clock_rate;
280 	writeq(clock_comp, clock->reg_base + PTP_CLOCK_COMP);
282 	clock->ptp_clock = ptp_clock_register(&clock->ptp_info, dev);
283 	if (IS_ERR(clock->ptp_clock)) {
284 		err = PTR_ERR(clock->ptp_clock);
288 	pci_set_drvdata(pdev, clock);
292 	clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG);
294 	writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG);
298 	devm_kfree(dev, clock);
313 	struct cavium_ptp *clock = pci_get_drvdata(pdev);
316 	if (IS_ERR_OR_NULL(clock))
319 	ptp_clock_unregister(clock->ptp_clock);
321 	clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG);
323 	writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG);