ethernet/broadcom/tg3.c

4440 		u32 bmcr, orig_bmcr;
4453 		bmcr = 0;
4460 			bmcr |= BMCR_SPEED100;
4464 			bmcr |= BMCR_SPEED1000;
4469 			bmcr |= BMCR_FULLDPLX;
4472 		    (bmcr != orig_bmcr)) {
4486 			tg3_writephy(tp, MII_BMCR, bmcr);
4884 		u32 aux_stat, bmcr;
4898 		bmcr = 0;
4900 			tg3_readphy(tp, MII_BMCR, &bmcr);
4901 			if (tg3_readphy(tp, MII_BMCR, &bmcr))
4903 			if (bmcr && bmcr != 0x7fff)
4917 			if ((bmcr & BMCR_ANENABLE) &&
4934 			if (!(bmcr & BMCR_ANENABLE) &&
5801 	u32 bmsr, bmcr;
5866 	err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5883 		if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5885 			bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5886 			tg3_writephy(tp, MII_BMCR, bmcr);
5897 		bmcr &= ~BMCR_SPEED1000;
5898 		new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5903 		if (new_bmcr != bmcr) {
5918 				tg3_writephy(tp, MII_BMCR, bmcr |
5925 			bmcr = new_bmcr;
5941 		if (bmcr & BMCR_FULLDPLX)
5949 		if (bmcr & BMCR_ANENABLE) {
6002 		u32 bmcr;
6004 		tg3_readphy(tp, MII_BMCR, &bmcr);
6005 		if (bmcr & BMCR_ANENABLE) {
6024 				bmcr &= ~BMCR_ANENABLE;
6025 				bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6026 				tg3_writephy(tp, MII_BMCR, bmcr);
6040 			u32 bmcr;
6043 			tg3_readphy(tp, MII_BMCR, &bmcr);
6044 			tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
8262 	u32 val, bmcr, mac_mode, ptest = 0;
8270 	bmcr = BMCR_FULLDPLX;
8275 		bmcr |= BMCR_SPEED100;
8281 			bmcr |= BMCR_SPEED100;
8284 			bmcr |= BMCR_SPEED1000;
8300 		bmcr |= BMCR_LOOPBACK;
8302 	tg3_writephy(tp, MII_BMCR, bmcr);
8306 		tg3_readphy(tp, MII_BMCR, &bmcr);
12479 		u32 bmcr;
12483 		tg3_readphy(tp, MII_BMCR, &bmcr);
12484 		if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12485 		    ((bmcr & BMCR_ANENABLE) ||
12487 			tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |