ethernet/broadcom/tg3.c

539 	 * to clear the interrupt bit in the GRC local ctrl register.
680 	u32 regbase, bit;
694 			bit = APE_LOCK_GRANT_DRIVER;
698 				bit = APE_LOCK_GRANT_DRIVER;
700 				bit = 1 << tp->pci_fn;
702 		tg3_ape_write32(tp, regbase + 4 * i, bit);
711 	u32 status, req, gnt, bit;
724 			bit = APE_LOCK_REQ_DRIVER;
726 			bit = 1 << tp->pci_fn;
732 		bit = APE_LOCK_REQ_DRIVER;
748 	tg3_ape_write32(tp, req + off, bit);
753 		if (status == bit)
761 	if (status != bit) {
763 		tg3_ape_write32(tp, gnt + off, bit);
772 	u32 gnt, bit;
785 			bit = APE_LOCK_GRANT_DRIVER;
787 			bit = 1 << tp->pci_fn;
793 		bit = APE_LOCK_GRANT_DRIVER;
804 	tg3_ape_write32(tp, gnt + 4 * locknum, bit);
1356 	/* OK, reset it, and poll the BMCR_RESET bit until it
2733 	/* Set Extended packet length bit (bit 14) on all chips that */
2739 		/* Set bit 14 with read-modify-write to preserve other bits */
2747 	/* Set phy register 0x10 bit 0 to high fifo elasticity to support
3278  * machine, the 32-bit value will be byteswapped.
4594 	/* Set Extended packet length bit */
4943 			u32 reg, bit;
4947 				bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4950 				bit = MII_TG3_EXT_STAT_MDIX;
4953 			if (!tg3_readphy(tp, reg, &val) && (val & bit))
5904 			/* BMCR_SPEED1000 is a reserved bit that needs
6178 	/* Frequency adjustment is performed using hardware with a 24 bit
7704 /* Test for DMA addresses > 40-bit */
7826 /* Workaround 4GB and 40-bit hardware DMA bugs. */
8886 /* To stop a block, clear the enable bit and poll till it
9048 	/* Make sure PCI-X relaxed ordering bit is clear. */
9061 		/* Chip reset on 5780 will reset MSI enable bit,
9144 	 * enable bit in PCI register 4 and the MSI enable bit
9164 	 * during chip reset when the memory enable bit in the PCI command
9842 		u32 bit;
9847 			bit = ~crc & 0x7f;
9848 			regidx = (bit & 0x60) >> 5;
9849 			bit &= 0x1f;
9850 			mc_filter[regidx] |= (1 << bit);
10067 	 * B3 tigon3 silicon.  This bit has no effect on any
10720 			/* only if the signal pre-emphasis bit is not set  */
12040 	 * Note that these counters wrap around at 4G on 32bit machines.
14430 			 * 16-bit value at offset 0xf2.  The tg3_nvram_read()
14437 			 * opposite the endianness of the CPU.  The 16-bit
15390 		/* bootcode if bit 18 is set */
15485  * configuration is a 32-bit value that straddles the alignment boundary.
15486  * We do two 32-bit reads and then shift and merge the results.
16367 	 * DMA addresses > 40-bit. This bridge may have other additional
16369 	 * Any tg3 device found behind the bridge will also need the 40-bit
16965 	 * change bit implementation, so we must use the
17378 			/* Set bit 23 to enable PCIX hw bug fix */
17405 		/* On 5700/5701 chips, we need to set this bit.
17411 		 * On 5703/5704 chips, this bit has been reassigned
17622 		strcat(str, ":32-bit");
17624 		strcat(str, ":64-bit");
17793 	 * device behind the EPB cannot support DMA addresses > 40-bit.
17794 	 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17795 	 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17816 				dev_err(&pdev->dev, "Unable to obtain 64 bit "
18016 	netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",