Lines Matching defs:wb_data
589 u32 *data = bnx2x_sp(bp, wb_data[0]);
624 u32 *data = bnx2x_sp(bp, wb_data[0]);
643 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
644 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
6721 val = *bnx2x_sp(bp, wb_data[0]);
6777 val = *bnx2x_sp(bp, wb_data[0]);
7464 val = *bnx2x_sp(bp, wb_data[0]);
8243 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
10442 u32 wb_data[2];
10455 wb_data[0] = REG_RD(bp, base_addr + offset);
10456 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10458 vals->bmac_val[0] = wb_data[0];
10459 vals->bmac_val[1] = wb_data[1];
10460 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10461 REG_WR(bp, vals->bmac_addr, wb_data[0]);
10462 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
15183 u32 wb_data[2];
15187 NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
15188 phc_cycles = wb_data[1];
15189 phc_cycles = (phc_cycles << 32) + wb_data[0];
15385 u32 wb_data[2];
15406 wb_data[0] = 0;
15407 wb_data[1] = 0;
15408 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);