broadcom/bnx2x/bnx2x_main.c

404 			  struct dmae_command *dmae, int msglvl)
406 	u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
409 	switch (dmae->opcode & DMAE_COMMAND_DST) {
415 			   dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
416 			   dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
417 			   dmae->comp_addr_hi, dmae->comp_addr_lo,
418 			   dmae->comp_val);
423 			   dmae->opcode, dmae->src_addr_lo >> 2,
424 			   dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
425 			   dmae->comp_addr_hi, dmae->comp_addr_lo,
426 			   dmae->comp_val);
433 			   dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
434 			   dmae->len, dmae->dst_addr_lo >> 2,
435 			   dmae->comp_addr_hi, dmae->comp_addr_lo,
436 			   dmae->comp_val);
441 			   dmae->opcode, dmae->src_addr_lo >> 2,
442 			   dmae->len, dmae->dst_addr_lo >> 2,
443 			   dmae->comp_addr_hi, dmae->comp_addr_lo,
444 			   dmae->comp_val);
451 			   dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
452 			   dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
453 			   dmae->comp_val);
458 			   dmae->opcode, dmae->src_addr_lo >> 2,
459 			   dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
460 			   dmae->comp_val);
466 		   i, *(((u32 *)dmae) + i));
470 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
477 		REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
519 				      struct dmae_command *dmae,
522 	memset(dmae, 0, sizeof(struct dmae_command));
525 	dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
529 	dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
530 	dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
531 	dmae->comp_val = DMAE_COMP_VAL;
534 /* issue a dmae command over the init-channel and wait for completion */
535 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
541 	bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
543 	/* Lock the dmae channel. Disable BHs to prevent a dead-lock
554 	bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
586 	struct dmae_command dmae;
599 	bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
602 	dmae.src_addr_lo = U64_LO(dma_addr);
603 	dmae.src_addr_hi = U64_HI(dma_addr);
604 	dmae.dst_addr_lo = dst_addr >> 2;
605 	dmae.dst_addr_hi = 0;
606 	dmae.len = len32;
609 	rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
621 	struct dmae_command dmae;
638 	bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
641 	dmae.src_addr_lo = src_addr >> 2;
642 	dmae.src_addr_hi = 0;
643 	dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
644 	dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
645 	dmae.len = len32;
648 	rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
7158  *		    dmae-operations (writing to pram for example.)
7528 	 * common phase, we need to enable it here before any dmae access are
9772 	 * respond. The write queue in PGLUE would stuck, dmae commands
10450 			 * use rd/wr since we cannot use dmae. This is safe
10861 	 * dmae transaction.