Lines Matching refs:bp
243 static void bnx2_init_napi(struct bnx2 *bp);
244 static void bnx2_del_napi(struct bnx2 *bp);
246 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
259 return bp->tx_ring_size - diff;
263 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
268 spin_lock_irqsave(&bp->indirect_lock, flags);
269 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
270 val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW);
271 spin_unlock_irqrestore(&bp->indirect_lock, flags);
276 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
280 spin_lock_irqsave(&bp->indirect_lock, flags);
281 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
282 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
283 spin_unlock_irqrestore(&bp->indirect_lock, flags);
287 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
289 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
293 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
295 return bnx2_reg_rd_ind(bp, bp->shmem_base + offset);
299 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
304 spin_lock_irqsave(&bp->indirect_lock, flags);
305 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
308 BNX2_WR(bp, BNX2_CTX_CTX_DATA, val);
309 BNX2_WR(bp, BNX2_CTX_CTX_CTRL,
312 val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL);
318 BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset);
319 BNX2_WR(bp, BNX2_CTX_DATA, val);
321 spin_unlock_irqrestore(&bp->indirect_lock, flags);
328 struct bnx2 *bp = netdev_priv(dev);
333 bnx2_reg_wr_ind(bp, io->offset, io->data);
336 io->data = bnx2_reg_rd_ind(bp, io->offset);
339 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
347 static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
349 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
350 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
353 if (bp->flags & BNX2_FLAG_USING_MSIX) {
356 sb_id = bp->irq_nvecs;
366 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
370 cp->irq_arr[0].status_blk_map = bp->status_blk_mapping;
378 struct bnx2 *bp = netdev_priv(dev);
379 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
387 if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN))
390 bp->cnic_data = data;
391 rcu_assign_pointer(bp->cnic_ops, ops);
396 bnx2_setup_cnic_irq_info(bp);
403 struct bnx2 *bp = netdev_priv(dev);
404 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
405 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
407 mutex_lock(&bp->cnic_lock);
410 RCU_INIT_POINTER(bp->cnic_ops, NULL);
411 mutex_unlock(&bp->cnic_lock);
418 struct bnx2 *bp = netdev_priv(dev);
419 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
425 cp->chip_id = bp->chip_id;
426 cp->pdev = bp->pdev;
427 cp->io_base = bp->regview;
436 bnx2_cnic_stop(struct bnx2 *bp)
441 mutex_lock(&bp->cnic_lock);
442 c_ops = rcu_dereference_protected(bp->cnic_ops,
443 lockdep_is_held(&bp->cnic_lock));
446 c_ops->cnic_ctl(bp->cnic_data, &info);
448 mutex_unlock(&bp->cnic_lock);
452 bnx2_cnic_start(struct bnx2 *bp)
457 mutex_lock(&bp->cnic_lock);
458 c_ops = rcu_dereference_protected(bp->cnic_ops,
459 lockdep_is_held(&bp->cnic_lock));
461 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
462 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
467 c_ops->cnic_ctl(bp->cnic_data, &info);
469 mutex_unlock(&bp->cnic_lock);
475 bnx2_cnic_stop(struct bnx2 *bp)
480 bnx2_cnic_start(struct bnx2 *bp)
487 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
492 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
493 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
496 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
497 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
502 val1 = (bp->phy_addr << 21) | (reg << 16) |
505 BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
510 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
514 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
530 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
531 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
534 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
535 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
544 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
549 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
550 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
553 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
554 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
559 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
562 BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
567 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
579 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
580 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
583 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
584 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
593 bnx2_disable_int(struct bnx2 *bp)
598 for (i = 0; i < bp->irq_nvecs; i++) {
599 bnapi = &bp->bnx2_napi[i];
600 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
603 BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
607 bnx2_enable_int(struct bnx2 *bp)
612 for (i = 0; i < bp->irq_nvecs; i++) {
613 bnapi = &bp->bnx2_napi[i];
615 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
620 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
624 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
628 bnx2_disable_int_sync(struct bnx2 *bp)
632 atomic_inc(&bp->intr_sem);
633 if (!netif_running(bp->dev))
636 bnx2_disable_int(bp);
637 for (i = 0; i < bp->irq_nvecs; i++)
638 synchronize_irq(bp->irq_tbl[i].vector);
642 bnx2_napi_disable(struct bnx2 *bp)
646 for (i = 0; i < bp->irq_nvecs; i++)
647 napi_disable(&bp->bnx2_napi[i].napi);
651 bnx2_napi_enable(struct bnx2 *bp)
655 for (i = 0; i < bp->irq_nvecs; i++)
656 napi_enable(&bp->bnx2_napi[i].napi);
660 bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)
663 bnx2_cnic_stop(bp);
664 if (netif_running(bp->dev)) {
665 bnx2_napi_disable(bp);
666 netif_tx_disable(bp->dev);
668 bnx2_disable_int_sync(bp);
669 netif_carrier_off(bp->dev); /* prevent tx timeout */
673 bnx2_netif_start(struct bnx2 *bp, bool start_cnic)
675 if (atomic_dec_and_test(&bp->intr_sem)) {
676 if (netif_running(bp->dev)) {
677 netif_tx_wake_all_queues(bp->dev);
678 spin_lock_bh(&bp->phy_lock);
679 if (bp->link_up)
680 netif_carrier_on(bp->dev);
681 spin_unlock_bh(&bp->phy_lock);
682 bnx2_napi_enable(bp);
683 bnx2_enable_int(bp);
685 bnx2_cnic_start(bp);
691 bnx2_free_tx_mem(struct bnx2 *bp)
695 for (i = 0; i < bp->num_tx_rings; i++) {
696 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
700 dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
711 bnx2_free_rx_mem(struct bnx2 *bp)
715 for (i = 0; i < bp->num_rx_rings; i++) {
716 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
720 for (j = 0; j < bp->rx_max_ring; j++) {
722 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
730 for (j = 0; j < bp->rx_max_pg_ring; j++) {
732 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
743 bnx2_alloc_tx_mem(struct bnx2 *bp)
747 for (i = 0; i < bp->num_tx_rings; i++) {
748 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
756 dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
765 bnx2_alloc_rx_mem(struct bnx2 *bp)
769 for (i = 0; i < bp->num_rx_rings; i++) {
770 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
775 vzalloc(array_size(SW_RXBD_RING_SIZE, bp->rx_max_ring));
779 for (j = 0; j < bp->rx_max_ring; j++) {
781 dma_alloc_coherent(&bp->pdev->dev,
790 if (bp->rx_pg_ring_size) {
793 bp->rx_max_pg_ring));
799 for (j = 0; j < bp->rx_max_pg_ring; j++) {
801 dma_alloc_coherent(&bp->pdev->dev,
816 struct bnx2 *bp = netdev_priv(dev);
818 if (bp->status_blk) {
819 dma_free_coherent(&bp->pdev->dev, bp->status_stats_size,
820 bp->status_blk,
821 bp->status_blk_mapping);
822 bp->status_blk = NULL;
823 bp->stats_blk = NULL;
832 struct bnx2 *bp = netdev_priv(dev);
836 if (bp->flags & BNX2_FLAG_MSIX_CAP)
839 bp->status_stats_size = status_blk_size +
841 status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size,
842 &bp->status_blk_mapping, GFP_KERNEL);
846 bp->status_blk = status_blk;
847 bp->stats_blk = status_blk + status_blk_size;
848 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
854 bnx2_free_mem(struct bnx2 *bp)
857 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
859 bnx2_free_tx_mem(bp);
860 bnx2_free_rx_mem(bp);
862 for (i = 0; i < bp->ctx_pages; i++) {
863 if (bp->ctx_blk[i]) {
864 dma_free_coherent(&bp->pdev->dev, BNX2_PAGE_SIZE,
865 bp->ctx_blk[i],
866 bp->ctx_blk_mapping[i]);
867 bp->ctx_blk[i] = NULL;
876 bnx2_alloc_mem(struct bnx2 *bp)
881 bnapi = &bp->bnx2_napi[0];
882 bnapi->status_blk.msi = bp->status_blk;
887 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
888 for (i = 1; i < bp->irq_nvecs; i++) {
891 bnapi = &bp->bnx2_napi[i];
893 sblk = (bp->status_blk + BNX2_SBLK_MSIX_ALIGN_SIZE * i);
903 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
904 bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE;
905 if (bp->ctx_pages == 0)
906 bp->ctx_pages = 1;
907 for (i = 0; i < bp->ctx_pages; i++) {
908 bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev,
910 &bp->ctx_blk_mapping[i],
912 if (!bp->ctx_blk[i])
917 err = bnx2_alloc_rx_mem(bp);
921 err = bnx2_alloc_tx_mem(bp);
928 bnx2_free_mem(bp);
933 bnx2_report_fw_link(struct bnx2 *bp)
937 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
940 if (bp->link_up) {
943 switch (bp->line_speed) {
945 if (bp->duplex == DUPLEX_HALF)
951 if (bp->duplex == DUPLEX_HALF)
957 if (bp->duplex == DUPLEX_HALF)
963 if (bp->duplex == DUPLEX_HALF)
972 if (bp->autoneg) {
975 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
976 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
979 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
988 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
992 bnx2_xceiver_str(struct bnx2 *bp)
994 return (bp->phy_port == PORT_FIBRE) ? "SerDes" :
995 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
1000 bnx2_report_link(struct bnx2 *bp)
1002 if (bp->link_up) {
1003 netif_carrier_on(bp->dev);
1004 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
1005 bnx2_xceiver_str(bp),
1006 bp->line_speed,
1007 bp->duplex == DUPLEX_FULL ? "full" : "half");
1009 if (bp->flow_ctrl) {
1010 if (bp->flow_ctrl & FLOW_CTRL_RX) {
1012 if (bp->flow_ctrl & FLOW_CTRL_TX)
1022 netif_carrier_off(bp->dev);
1023 netdev_err(bp->dev, "NIC %s Link is Down\n",
1024 bnx2_xceiver_str(bp));
1027 bnx2_report_fw_link(bp);
1031 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1035 bp->flow_ctrl = 0;
1036 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1039 if (bp->duplex == DUPLEX_FULL) {
1040 bp->flow_ctrl = bp->req_flow_ctrl;
1045 if (bp->duplex != DUPLEX_FULL) {
1049 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1050 (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {
1053 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1055 bp->flow_ctrl |= FLOW_CTRL_TX;
1057 bp->flow_ctrl |= FLOW_CTRL_RX;
1061 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1062 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1064 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1085 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1088 bp->flow_ctrl = FLOW_CTRL_RX;
1093 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1101 bp->flow_ctrl = FLOW_CTRL_TX;
1107 bnx2_5709s_linkup(struct bnx2 *bp)
1111 bp->link_up = 1;
1113 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1114 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1115 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1117 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1118 bp->line_speed = bp->req_line_speed;
1119 bp->duplex = bp->req_duplex;
1125 bp->line_speed = SPEED_10;
1128 bp->line_speed = SPEED_100;
1132 bp->line_speed = SPEED_1000;
1135 bp->line_speed = SPEED_2500;
1139 bp->duplex = DUPLEX_FULL;
1141 bp->duplex = DUPLEX_HALF;
1146 bnx2_5708s_linkup(struct bnx2 *bp)
1150 bp->link_up = 1;
1151 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1154 bp->line_speed = SPEED_10;
1157 bp->line_speed = SPEED_100;
1160 bp->line_speed = SPEED_1000;
1163 bp->line_speed = SPEED_2500;
1167 bp->duplex = DUPLEX_FULL;
1169 bp->duplex = DUPLEX_HALF;
1175 bnx2_5706s_linkup(struct bnx2 *bp)
1179 bp->link_up = 1;
1180 bp->line_speed = SPEED_1000;
1182 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1184 bp->duplex = DUPLEX_FULL;
1187 bp->duplex = DUPLEX_HALF;
1194 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1195 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1201 bp->duplex = DUPLEX_FULL;
1204 bp->duplex = DUPLEX_HALF;
1212 bnx2_copper_linkup(struct bnx2 *bp)
1216 bp->phy_flags &= ~BNX2_PHY_FLAG_MDIX;
1218 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1222 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1223 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1227 bp->line_speed = SPEED_1000;
1228 bp->duplex = DUPLEX_FULL;
1231 bp->line_speed = SPEED_1000;
1232 bp->duplex = DUPLEX_HALF;
1235 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1236 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1240 bp->line_speed = SPEED_100;
1241 bp->duplex = DUPLEX_FULL;
1244 bp->line_speed = SPEED_100;
1245 bp->duplex = DUPLEX_HALF;
1248 bp->line_speed = SPEED_10;
1249 bp->duplex = DUPLEX_FULL;
1252 bp->line_speed = SPEED_10;
1253 bp->duplex = DUPLEX_HALF;
1256 bp->line_speed = 0;
1257 bp->link_up = 0;
1263 bp->line_speed = SPEED_100;
1266 bp->line_speed = SPEED_10;
1269 bp->duplex = DUPLEX_FULL;
1272 bp->duplex = DUPLEX_HALF;
1276 if (bp->link_up) {
1279 bnx2_read_phy(bp, MII_BNX2_EXT_STATUS, &ext_status);
1281 bp->phy_flags |= BNX2_PHY_FLAG_MDIX;
1288 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1296 if (bp->flow_ctrl & FLOW_CTRL_TX)
1299 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1303 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1308 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1311 bnx2_init_rx_context(bp, cid);
1316 bnx2_set_mac_link(struct bnx2 *bp)
1320 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1321 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1322 (bp->duplex == DUPLEX_HALF)) {
1323 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1327 val = BNX2_RD(bp, BNX2_EMAC_MODE);
1333 if (bp->link_up) {
1334 switch (bp->line_speed) {
1336 if (BNX2_CHIP(bp) != BNX2_CHIP_5706) {
1357 if (bp->duplex == DUPLEX_HALF)
1359 BNX2_WR(bp, BNX2_EMAC_MODE, val);
1362 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1364 if (bp->flow_ctrl & FLOW_CTRL_RX)
1365 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1366 BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1369 val = BNX2_RD(bp, BNX2_EMAC_TX_MODE);
1372 if (bp->flow_ctrl & FLOW_CTRL_TX)
1374 BNX2_WR(bp, BNX2_EMAC_TX_MODE, val);
1377 BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1379 bnx2_init_all_rx_contexts(bp);
1383 bnx2_enable_bmsr1(struct bnx2 *bp)
1385 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1386 (BNX2_CHIP(bp) == BNX2_CHIP_5709))
1387 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1392 bnx2_disable_bmsr1(struct bnx2 *bp)
1394 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1395 (BNX2_CHIP(bp) == BNX2_CHIP_5709))
1396 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1401 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1406 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1409 if (bp->autoneg & AUTONEG_SPEED)
1410 bp->advertising |= ADVERTISED_2500baseX_Full;
1412 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
1413 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1415 bnx2_read_phy(bp, bp->mii_up1, &up1);
1418 bnx2_write_phy(bp, bp->mii_up1, up1);
1422 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
1423 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1430 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1435 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1438 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
1439 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1441 bnx2_read_phy(bp, bp->mii_up1, &up1);
1444 bnx2_write_phy(bp, bp->mii_up1, up1);
1448 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
1449 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1456 bnx2_enable_forced_2g5(struct bnx2 *bp)
1461 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1464 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
1467 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1469 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1473 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1476 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1478 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1480 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {
1481 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1491 if (bp->autoneg & AUTONEG_SPEED) {
1493 if (bp->req_duplex == DUPLEX_FULL)
1496 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1500 bnx2_disable_forced_2g5(struct bnx2 *bp)
1505 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1508 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
1511 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1513 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1515 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1518 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1520 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1522 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {
1523 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1533 if (bp->autoneg & AUTONEG_SPEED)
1535 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1539 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1543 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1544 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1546 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1548 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1552 bnx2_set_link(struct bnx2 *bp)
1557 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1558 bp->link_up = 1;
1562 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1565 link_up = bp->link_up;
1567 bnx2_enable_bmsr1(bp);
1568 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1569 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1570 bnx2_disable_bmsr1(bp);
1572 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1573 (BNX2_CHIP(bp) == BNX2_CHIP_5706)) {
1576 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1577 bnx2_5706s_force_link_dn(bp, 0);
1578 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1580 val = BNX2_RD(bp, BNX2_EMAC_STATUS);
1582 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1583 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1584 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1594 bp->link_up = 1;
1596 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1597 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
1598 bnx2_5706s_linkup(bp);
1599 else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)
1600 bnx2_5708s_linkup(bp);
1601 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
1602 bnx2_5709s_linkup(bp);
1605 bnx2_copper_linkup(bp);
1607 bnx2_resolve_flow_ctrl(bp);
1610 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1611 (bp->autoneg & AUTONEG_SPEED))
1612 bnx2_disable_forced_2g5(bp);
1614 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1617 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1619 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1621 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1623 bp->link_up = 0;
1626 if (bp->link_up != link_up) {
1627 bnx2_report_link(bp);
1630 bnx2_set_mac_link(bp);
1636 bnx2_reset_phy(struct bnx2 *bp)
1641 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1647 bnx2_read_phy(bp, bp->mii_bmcr, ®);
1660 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1664 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1667 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1674 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1675 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1682 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1683 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1696 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1697 __releases(&bp->phy_lock)
1698 __acquires(&bp->phy_lock)
1702 pause_adv = bnx2_phy_get_pause_adv(bp);
1704 if (bp->autoneg & AUTONEG_SPEED) {
1706 if (bp->advertising & ADVERTISED_10baseT_Half)
1708 if (bp->advertising & ADVERTISED_10baseT_Full)
1710 if (bp->advertising & ADVERTISED_100baseT_Half)
1712 if (bp->advertising & ADVERTISED_100baseT_Full)
1714 if (bp->advertising & ADVERTISED_1000baseT_Full)
1716 if (bp->advertising & ADVERTISED_2500baseX_Full)
1719 if (bp->req_line_speed == SPEED_2500)
1721 else if (bp->req_line_speed == SPEED_1000)
1723 else if (bp->req_line_speed == SPEED_100) {
1724 if (bp->req_duplex == DUPLEX_FULL)
1728 } else if (bp->req_line_speed == SPEED_10) {
1729 if (bp->req_duplex == DUPLEX_FULL)
1745 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1747 spin_unlock_bh(&bp->phy_lock);
1748 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1749 spin_lock_bh(&bp->phy_lock);
1755 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1756 __releases(&bp->phy_lock)
1757 __acquires(&bp->phy_lock)
1762 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1763 return bnx2_setup_remote_phy(bp, port);
1765 if (!(bp->autoneg & AUTONEG_SPEED)) {
1769 if (bp->req_line_speed == SPEED_2500) {
1770 if (!bnx2_test_and_enable_2g5(bp))
1772 } else if (bp->req_line_speed == SPEED_1000) {
1773 if (bnx2_test_and_disable_2g5(bp))
1776 bnx2_read_phy(bp, bp->mii_adv, &adv);
1779 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1783 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
1784 if (bp->req_line_speed == SPEED_2500)
1785 bnx2_enable_forced_2g5(bp);
1786 else if (bp->req_line_speed == SPEED_1000) {
1787 bnx2_disable_forced_2g5(bp);
1791 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {
1792 if (bp->req_line_speed == SPEED_2500)
1798 if (bp->req_duplex == DUPLEX_FULL) {
1808 if (bp->link_up) {
1809 bnx2_write_phy(bp, bp->mii_adv, adv &
1812 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1815 bp->link_up = 0;
1816 netif_carrier_off(bp->dev);
1817 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1818 bnx2_report_link(bp);
1820 bnx2_write_phy(bp, bp->mii_adv, adv);
1821 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1823 bnx2_resolve_flow_ctrl(bp);
1824 bnx2_set_mac_link(bp);
1829 bnx2_test_and_enable_2g5(bp);
1831 if (bp->advertising & ADVERTISED_1000baseT_Full)
1834 new_adv |= bnx2_phy_get_pause_adv(bp);
1836 bnx2_read_phy(bp, bp->mii_adv, &adv);
1837 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1839 bp->serdes_an_pending = 0;
1842 if (bp->link_up) {
1843 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1844 spin_unlock_bh(&bp->phy_lock);
1846 spin_lock_bh(&bp->phy_lock);
1849 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1850 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1860 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1861 bp->serdes_an_pending = 1;
1862 mod_timer(&bp->timer, jiffies + bp->current_interval);
1864 bnx2_resolve_flow_ctrl(bp);
1865 bnx2_set_mac_link(bp);
1872 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1887 bnx2_set_default_remote_link(struct bnx2 *bp)
1891 if (bp->phy_port == PORT_TP)
1892 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1894 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1897 bp->req_line_speed = 0;
1898 bp->autoneg |= AUTONEG_SPEED;
1899 bp->advertising = ADVERTISED_Autoneg;
1901 bp->advertising |= ADVERTISED_10baseT_Half;
1903 bp->advertising |= ADVERTISED_10baseT_Full;
1905 bp->advertising |= ADVERTISED_100baseT_Half;
1907 bp->advertising |= ADVERTISED_100baseT_Full;
1909 bp->advertising |= ADVERTISED_1000baseT_Full;
1911 bp->advertising |= ADVERTISED_2500baseX_Full;
1913 bp->autoneg = 0;
1914 bp->advertising = 0;
1915 bp->req_duplex = DUPLEX_FULL;
1917 bp->req_line_speed = SPEED_10;
1919 bp->req_duplex = DUPLEX_HALF;
1922 bp->req_line_speed = SPEED_100;
1924 bp->req_duplex = DUPLEX_HALF;
1927 bp->req_line_speed = SPEED_1000;
1929 bp->req_line_speed = SPEED_2500;
1934 bnx2_set_default_link(struct bnx2 *bp)
1936 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1937 bnx2_set_default_remote_link(bp);
1941 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1942 bp->req_line_speed = 0;
1943 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1946 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1948 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1951 bp->autoneg = 0;
1952 bp->req_line_speed = bp->line_speed = SPEED_1000;
1953 bp->req_duplex = DUPLEX_FULL;
1956 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1960 bnx2_send_heart_beat(struct bnx2 *bp)
1965 spin_lock(&bp->indirect_lock);
1966 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1967 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1968 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1969 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1970 spin_unlock(&bp->indirect_lock);
1974 bnx2_remote_phy_event(struct bnx2 *bp)
1977 u8 link_up = bp->link_up;
1980 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1983 bnx2_send_heart_beat(bp);
1988 bp->link_up = 0;
1992 bp->link_up = 1;
1994 bp->duplex = DUPLEX_FULL;
1997 bp->duplex = DUPLEX_HALF;
2000 bp->line_speed = SPEED_10;
2003 bp->duplex = DUPLEX_HALF;
2007 bp->line_speed = SPEED_100;
2010 bp->duplex = DUPLEX_HALF;
2013 bp->line_speed = SPEED_1000;
2016 bp->duplex = DUPLEX_HALF;
2019 bp->line_speed = SPEED_2500;
2022 bp->line_speed = 0;
2026 bp->flow_ctrl = 0;
2027 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2029 if (bp->duplex == DUPLEX_FULL)
2030 bp->flow_ctrl = bp->req_flow_ctrl;
2033 bp->flow_ctrl |= FLOW_CTRL_TX;
2035 bp->flow_ctrl |= FLOW_CTRL_RX;
2038 old_port = bp->phy_port;
2040 bp->phy_port = PORT_FIBRE;
2042 bp->phy_port = PORT_TP;
2044 if (old_port != bp->phy_port)
2045 bnx2_set_default_link(bp);
2048 if (bp->link_up != link_up)
2049 bnx2_report_link(bp);
2051 bnx2_set_mac_link(bp);
2055 bnx2_set_remote_link(struct bnx2 *bp)
2059 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
2062 bnx2_remote_phy_event(bp);
2066 bnx2_send_heart_beat(bp);
2073 bnx2_setup_copper_phy(struct bnx2 *bp)
2074 __releases(&bp->phy_lock)
2075 __acquires(&bp->phy_lock)
2080 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
2082 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
2086 new_adv = ADVERTISE_CSMA | ethtool_adv_to_mii_adv_t(bp->advertising);
2088 if (bp->autoneg & AUTONEG_SPEED) {
2092 new_adv |= bnx2_phy_get_pause_adv(bp);
2094 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2097 new_adv1000 |= ethtool_adv_to_mii_ctrl1000_t(bp->advertising);
2102 bnx2_write_phy(bp, bp->mii_adv, new_adv);
2103 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000);
2104 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
2107 else if (bp->link_up) {
2111 bnx2_resolve_flow_ctrl(bp);
2112 bnx2_set_mac_link(bp);
2119 bnx2_write_phy(bp, bp->mii_adv, new_adv);
2122 if (bp->req_line_speed == SPEED_100) {
2125 if (bp->req_duplex == DUPLEX_FULL) {
2131 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2132 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2136 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
2137 spin_unlock_bh(&bp->phy_lock);
2139 spin_lock_bh(&bp->phy_lock);
2141 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2142 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2145 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
2152 bp->line_speed = bp->req_line_speed;
2153 bp->duplex = bp->req_duplex;
2154 bnx2_resolve_flow_ctrl(bp);
2155 bnx2_set_mac_link(bp);
2158 bnx2_resolve_flow_ctrl(bp);
2159 bnx2_set_mac_link(bp);
2165 bnx2_setup_phy(struct bnx2 *bp, u8 port)
2166 __releases(&bp->phy_lock)
2167 __acquires(&bp->phy_lock)
2169 if (bp->loopback == MAC_LOOPBACK)
2172 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2173 return bnx2_setup_serdes_phy(bp, port);
2176 return bnx2_setup_copper_phy(bp);
2181 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
2185 bp->mii_bmcr = MII_BMCR + 0x10;
2186 bp->mii_bmsr = MII_BMSR + 0x10;
2187 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2188 bp->mii_adv = MII_ADVERTISE + 0x10;
2189 bp->mii_lpa = MII_LPA + 0x10;
2190 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2192 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2193 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2195 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2197 bnx2_reset_phy(bp);
2199 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2201 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2204 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2206 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2207 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2208 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2212 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2214 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2215 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2217 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2219 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2223 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2225 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2231 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2236 bnx2_reset_phy(bp);
2238 bp->mii_up1 = BCM5708S_UP1;
2240 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2241 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2242 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2244 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2246 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2248 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2250 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2252 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2253 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2255 bnx2_write_phy(bp, BCM5708S_UP1, val);
2258 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||
2259 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||
2260 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1)) {
2262 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2264 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2266 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2267 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2270 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2276 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2278 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2280 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2281 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2289 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2292 bnx2_reset_phy(bp);
2294 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2296 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
2297 BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2299 if (bp->dev->mtu > ETH_DATA_LEN) {
2303 bnx2_write_phy(bp, 0x18, 0x7);
2304 bnx2_read_phy(bp, 0x18, &val);
2305 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2307 bnx2_write_phy(bp, 0x1c, 0x6c00);
2308 bnx2_read_phy(bp, 0x1c, &val);
2309 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2314 bnx2_write_phy(bp, 0x18, 0x7);
2315 bnx2_read_phy(bp, 0x18, &val);
2316 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2318 bnx2_write_phy(bp, 0x1c, 0x6c00);
2319 bnx2_read_phy(bp, 0x1c, &val);
2320 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2327 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2332 bnx2_reset_phy(bp);
2334 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2335 bnx2_write_phy(bp, 0x18, 0x0c00);
2336 bnx2_write_phy(bp, 0x17, 0x000a);
2337 bnx2_write_phy(bp, 0x15, 0x310b);
2338 bnx2_write_phy(bp, 0x17, 0x201f);
2339 bnx2_write_phy(bp, 0x15, 0x9506);
2340 bnx2_write_phy(bp, 0x17, 0x401f);
2341 bnx2_write_phy(bp, 0x15, 0x14e2);
2342 bnx2_write_phy(bp, 0x18, 0x0400);
2345 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2346 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2348 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2350 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2353 if (bp->dev->mtu > ETH_DATA_LEN) {
2355 bnx2_write_phy(bp, 0x18, 0x7);
2356 bnx2_read_phy(bp, 0x18, &val);
2357 bnx2_write_phy(bp, 0x18, val | 0x4000);
2359 bnx2_read_phy(bp, 0x10, &val);
2360 bnx2_write_phy(bp, 0x10, val | 0x1);
2363 bnx2_write_phy(bp, 0x18, 0x7);
2364 bnx2_read_phy(bp, 0x18, &val);
2365 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2367 bnx2_read_phy(bp, 0x10, &val);
2368 bnx2_write_phy(bp, 0x10, val & ~0x1);
2372 bnx2_write_phy(bp, MII_BNX2_AUX_CTL, AUX_CTL_MISC_CTL);
2373 bnx2_read_phy(bp, MII_BNX2_AUX_CTL, &val);
2377 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
2380 bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val);
2386 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2387 __releases(&bp->phy_lock)
2388 __acquires(&bp->phy_lock)
2393 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2394 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2396 bp->mii_bmcr = MII_BMCR;
2397 bp->mii_bmsr = MII_BMSR;
2398 bp->mii_bmsr1 = MII_BMSR;
2399 bp->mii_adv = MII_ADVERTISE;
2400 bp->mii_lpa = MII_LPA;
2402 BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2404 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2407 bnx2_read_phy(bp, MII_PHYSID1, &val);
2408 bp->phy_id = val << 16;
2409 bnx2_read_phy(bp, MII_PHYSID2, &val);
2410 bp->phy_id |= val & 0xffff;
2412 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2413 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
2414 rc = bnx2_init_5706s_phy(bp, reset_phy);
2415 else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)
2416 rc = bnx2_init_5708s_phy(bp, reset_phy);
2417 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
2418 rc = bnx2_init_5709s_phy(bp, reset_phy);
2421 rc = bnx2_init_copper_phy(bp, reset_phy);
2426 rc = bnx2_setup_phy(bp, bp->phy_port);
2432 bnx2_set_mac_loopback(struct bnx2 *bp)
2436 mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);
2439 BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);
2440 bp->link_up = 1;
2447 bnx2_set_phy_loopback(struct bnx2 *bp)
2452 spin_lock_bh(&bp->phy_lock);
2453 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2455 spin_unlock_bh(&bp->phy_lock);
2460 if (bnx2_test_link(bp) == 0)
2465 mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);
2471 BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);
2472 bp->link_up = 1;
2477 bnx2_dump_mcp_state(struct bnx2 *bp)
2479 struct net_device *dev = bp->dev;
2483 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
2491 bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
2493 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE),
2494 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE),
2495 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK));
2497 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2498 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2499 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION));
2502 bnx2_shmem_rd(bp, BNX2_DRV_MB),
2503 bnx2_shmem_rd(bp, BNX2_FW_MB),
2504 bnx2_shmem_rd(bp, BNX2_LINK_STATUS));
2505 pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB));
2507 bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE),
2508 bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE));
2510 bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION));
2511 DP_SHMEM_LINE(bp, BNX2_BC_RESET_TYPE);
2512 DP_SHMEM_LINE(bp, 0x3cc);
2513 DP_SHMEM_LINE(bp, 0x3dc);
2514 DP_SHMEM_LINE(bp, 0x3ec);
2515 netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc));
2520 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2525 bp->fw_wr_seq++;
2526 msg_data |= bp->fw_wr_seq;
2527 bp->fw_last_msg = msg_data;
2529 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2538 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2551 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2554 bnx2_dump_mcp_state(bp);
2567 bnx2_init_5709_context(struct bnx2 *bp)
2574 BNX2_WR(bp, BNX2_CTX_COMMAND, val);
2576 val = BNX2_RD(bp, BNX2_CTX_COMMAND);
2584 for (i = 0; i < bp->ctx_pages; i++) {
2587 if (bp->ctx_blk[i])
2588 memset(bp->ctx_blk[i], 0, BNX2_PAGE_SIZE);
2592 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2593 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2595 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2596 (u64) bp->ctx_blk_mapping[i] >> 32);
2597 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2601 val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2615 bnx2_init_context(struct bnx2 *bp)
2626 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
2647 BNX2_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2648 BNX2_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2652 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2658 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2668 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2674 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2676 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2679 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2689 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2700 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2707 bnx2_set_mac_addr(struct bnx2 *bp, const u8 *mac_addr, u32 pos)
2713 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2718 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2722 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
2732 mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE,
2734 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
2747 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2755 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping),
2763 bnx2_alloc_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
2771 data = kmalloc(bp->rx_buf_size, gfp);
2775 mapping = dma_map_single(&bp->pdev->dev,
2777 bp->rx_buf_use_size,
2779 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
2790 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2796 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2806 BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2808 BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2816 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2818 spin_lock(&bp->phy_lock);
2820 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2821 bnx2_set_link(bp);
2822 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2823 bnx2_set_remote_link(bp);
2825 spin_unlock(&bp->phy_lock);
2842 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2850 index = (bnapi - bp->bnx2_napi);
2851 txq = netdev_get_tx_queue(bp->dev, index);
2883 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
2895 dma_unmap_page(&bp->pdev->dev,
2925 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2928 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2937 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2994 bnx2_reuse_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
3003 dma_sync_single_for_device(&bp->pdev->dev,
3007 rxr->rx_prod_bseq += bp->rx_buf_use_size;
3024 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u8 *data,
3032 err = bnx2_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
3034 bnx2_reuse_rx_data(bp, rxr, data, (u16) (ring_idx >> 16), prod);
3040 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3045 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
3075 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
3100 err = bnx2_alloc_rx_page(bp, rxr,
3106 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
3111 dma_unmap_page(&bp->pdev->dev, mapping_old,
3141 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
3180 dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr,
3195 } else if (len > bp->rx_jumbo_thresh) {
3196 hdr_len = bp->rx_jumbo_thresh;
3206 bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,
3213 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3220 if (len <= bp->rx_copy_thresh) {
3221 skb = netdev_alloc_skb(bp->dev, len + 6);
3223 bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,
3235 bnx2_reuse_rx_data(bp, rxr, data,
3239 skb = bnx2_rx_skb(bp, rxr, data, len, hdr_len, dma_addr,
3245 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG))
3248 skb->protocol = eth_type_trans(skb, bp->dev);
3250 if (len > (bp->dev->mtu + ETH_HLEN) &&
3260 if ((bp->dev->features & NETIF_F_RXCSUM) &&
3268 if ((bp->dev->features & NETIF_F_RXHASH) &&
3274 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3295 BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3297 BNX2_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3299 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3312 struct bnx2 *bp = bnapi->bp;
3315 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3320 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3332 struct bnx2 *bp = bnapi->bp;
3337 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3349 struct bnx2 *bp = bnapi->bp;
3359 (BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3363 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3370 BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3373 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3420 bnx2_chk_missed_msi(struct bnx2 *bp)
3422 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3426 msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3430 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3431 BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3433 BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3434 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3438 bp->idle_chk_status_idx = bnapi->last_status_idx;
3442 static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3450 c_ops = rcu_dereference(bp->cnic_ops);
3452 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3458 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3467 bnx2_phy_int(bp, bnapi);
3472 BNX2_WR(bp, BNX2_HC_COMMAND,
3473 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3474 BNX2_RD(bp, BNX2_HC_COMMAND);
3478 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3485 bnx2_tx_int(bp, bnapi, 0);
3488 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3496 struct bnx2 *bp = bnapi->bp;
3501 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3511 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3523 struct bnx2 *bp = bnapi->bp;
3528 bnx2_poll_link(bp, bnapi);
3530 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3533 bnx2_poll_cnic(bp, bnapi);
3548 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3549 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3554 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3559 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3575 struct bnx2 *bp = netdev_priv(dev);
3583 spin_lock_bh(&bp->phy_lock);
3585 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3589 (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3599 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3622 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3637 bnx2_set_mac_addr(bp, ha->addr,
3646 if (rx_mode != bp->rx_mode) {
3647 bp->rx_mode = rx_mode;
3648 BNX2_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3651 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3652 BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3653 BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3655 spin_unlock_bh(&bp->phy_lock);
3685 static void bnx2_release_firmware(struct bnx2 *bp)
3687 if (bp->rv2p_firmware) {
3688 release_firmware(bp->mips_firmware);
3689 release_firmware(bp->rv2p_firmware);
3690 bp->rv2p_firmware = NULL;
3694 static int bnx2_request_uncached_firmware(struct bnx2 *bp)
3701 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
3703 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A0) ||
3704 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A1))
3713 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3719 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3724 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3725 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3726 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3727 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3728 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3729 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3730 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3731 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3736 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3737 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3738 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3747 release_firmware(bp->rv2p_firmware);
3748 bp->rv2p_firmware = NULL;
3750 release_firmware(bp->mips_firmware);
3754 static int bnx2_request_firmware(struct bnx2 *bp)
3756 return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp);
3772 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3783 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3794 BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3796 BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3800 BNX2_WR(bp, addr, val);
3803 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3810 BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3813 BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3816 BNX2_WR(bp, addr, val);
3822 BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3825 BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3832 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3841 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3843 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3844 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3850 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3857 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3864 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3871 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3878 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3885 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3889 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3892 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3895 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3897 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3898 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3902 bnx2_init_cpus(struct bnx2 *bp)
3905 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3907 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3910 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3911 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
3914 load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
3917 load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
3920 load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
3923 load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
3926 load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
3930 bnx2_setup_wol(struct bnx2 *bp)
3935 if (bp->wol) {
3939 autoneg = bp->autoneg;
3940 advertising = bp->advertising;
3942 if (bp->phy_port == PORT_TP) {
3943 bp->autoneg = AUTONEG_SPEED;
3944 bp->advertising = ADVERTISED_10baseT_Half |
3951 spin_lock_bh(&bp->phy_lock);
3952 bnx2_setup_phy(bp, bp->phy_port);
3953 spin_unlock_bh(&bp->phy_lock);
3955 bp->autoneg = autoneg;
3956 bp->advertising = advertising;
3958 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3960 val = BNX2_RD(bp, BNX2_EMAC_MODE);
3967 if (bp->phy_port == PORT_TP) {
3971 if (bp->line_speed == SPEED_2500)
3975 BNX2_WR(bp, BNX2_EMAC_MODE, val);
3979 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3982 BNX2_WR(bp, BNX2_EMAC_RX_MODE, BNX2_EMAC_RX_MODE_SORT_MODE);
3985 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3986 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val);
3987 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA);
3990 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3995 val = BNX2_RD(bp, BNX2_RPM_CONFIG);
3997 BNX2_WR(bp, BNX2_RPM_CONFIG, val);
4004 if (!(bp->flags & BNX2_FLAG_NO_WOL)) {
4008 if (bp->fw_last_msg || BNX2_CHIP(bp) != BNX2_CHIP_5709) {
4009 bnx2_fw_sync(bp, wol_msg, 1, 0);
4015 val = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
4016 bnx2_shmem_wr(bp, BNX2_PORT_FEATURE,
4018 bnx2_fw_sync(bp, wol_msg, 1, 0);
4019 bnx2_shmem_wr(bp, BNX2_PORT_FEATURE, val);
4025 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
4031 pci_enable_wake(bp->pdev, PCI_D0, false);
4032 pci_set_power_state(bp->pdev, PCI_D0);
4034 val = BNX2_RD(bp, BNX2_EMAC_MODE);
4037 BNX2_WR(bp, BNX2_EMAC_MODE, val);
4039 val = BNX2_RD(bp, BNX2_RPM_CONFIG);
4041 BNX2_WR(bp, BNX2_RPM_CONFIG, val);
4045 bnx2_setup_wol(bp);
4046 pci_wake_from_d3(bp->pdev, bp->wol);
4047 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||
4048 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) {
4050 if (bp->wol)
4051 pci_set_power_state(bp->pdev, PCI_D3hot);
4055 if (!bp->fw_last_msg && BNX2_CHIP(bp) == BNX2_CHIP_5709) {
4062 val = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
4065 bnx2_shmem_wr(bp, BNX2_BC_STATE_CONDITION, val);
4067 pci_set_power_state(bp->pdev, PCI_D3hot);
4081 bnx2_acquire_nvram_lock(struct bnx2 *bp)
4087 BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4089 val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
4103 bnx2_release_nvram_lock(struct bnx2 *bp)
4109 BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4112 val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
4127 bnx2_enable_nvram_write(struct bnx2 *bp)
4131 val = BNX2_RD(bp, BNX2_MISC_CFG);
4132 BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4134 if (bp->flash_info->flags & BNX2_NV_WREN) {
4137 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4138 BNX2_WR(bp, BNX2_NVM_COMMAND,
4144 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
4156 bnx2_disable_nvram_write(struct bnx2 *bp)
4160 val = BNX2_RD(bp, BNX2_MISC_CFG);
4161 BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4166 bnx2_enable_nvram_access(struct bnx2 *bp)
4170 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4172 BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4177 bnx2_disable_nvram_access(struct bnx2 *bp)
4181 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4183 BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4189 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4194 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
4203 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4206 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4209 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
4217 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
4229 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4238 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4239 offset = ((offset / bp->flash_info->page_size) <<
4240 bp->flash_info->page_bits) +
4241 (offset % bp->flash_info->page_size);
4245 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4248 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4251 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
4259 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
4261 __be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ));
4274 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4284 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4285 offset = ((offset / bp->flash_info->page_size) <<
4286 bp->flash_info->page_bits) +
4287 (offset % bp->flash_info->page_size);
4291 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4296 BNX2_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
4299 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4302 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
4308 if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4318 bnx2_init_nvram(struct bnx2 *bp)
4324 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
4325 bp->flash_info = &flash_5709;
4330 val = BNX2_RD(bp, BNX2_NVM_CFG1);
4341 bp->flash_info = flash;
4359 bp->flash_info = flash;
4362 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4366 bnx2_enable_nvram_access(bp);
4369 BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1);
4370 BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2);
4371 BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3);
4372 BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4375 bnx2_disable_nvram_access(bp);
4376 bnx2_release_nvram_lock(bp);
4384 bp->flash_info = NULL;
4390 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4393 bp->flash_size = val;
4395 bp->flash_size = bp->flash_info->total_size;
4401 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4411 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4415 bnx2_enable_nvram_access(bp);
4439 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4464 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4477 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4485 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4497 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4503 bnx2_disable_nvram_access(bp);
4505 bnx2_release_nvram_lock(bp);
4511 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4529 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4536 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4554 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4570 page_start -= (page_start % bp->flash_info->page_size);
4572 page_end = page_start + bp->flash_info->page_size;
4580 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4584 bnx2_enable_nvram_access(bp);
4587 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4592 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4593 if (j == (bp->flash_info->page_size - 4)) {
4596 rc = bnx2_nvram_read_dword(bp,
4609 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4615 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4617 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4621 bnx2_enable_nvram_write(bp);
4626 rc = bnx2_nvram_write_dword(bp, addr,
4639 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4644 rc = bnx2_nvram_write_dword(bp, addr, buf,
4656 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4663 rc = bnx2_nvram_write_dword(bp, addr,
4674 bnx2_disable_nvram_write(bp);
4677 bnx2_disable_nvram_access(bp);
4678 bnx2_release_nvram_lock(bp);
4691 bnx2_init_fw_cap(struct bnx2 *bp)
4695 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4696 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4698 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4699 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4701 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4706 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4710 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4714 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4716 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4718 bp->phy_port = PORT_FIBRE;
4720 bp->phy_port = PORT_TP;
4726 if (netif_running(bp->dev) && sig)
4727 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4731 bnx2_setup_msix_tbl(struct bnx2 *bp)
4733 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4735 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4736 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4740 bnx2_wait_dma_complete(struct bnx2 *bp)
4749 if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||
4750 (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {
4751 BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4756 val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4759 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4761 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4762 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4766 val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);
4777 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4785 bnx2_wait_dma_complete(bp);
4788 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4792 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4797 val = BNX2_RD(bp, BNX2_MISC_ID);
4799 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
4800 BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4801 BNX2_RD(bp, BNX2_MISC_COMMAND);
4807 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4815 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4821 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||
4822 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1))
4827 val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4842 val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0);
4849 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4853 spin_lock_bh(&bp->phy_lock);
4854 old_port = bp->phy_port;
4855 bnx2_init_fw_cap(bp);
4856 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4857 old_port != bp->phy_port)
4858 bnx2_set_default_remote_link(bp);
4859 spin_unlock_bh(&bp->phy_lock);
4861 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
4864 BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4867 rc = bnx2_alloc_bad_rbuf(bp);
4870 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4871 bnx2_setup_msix_tbl(bp);
4873 BNX2_WR(bp, BNX2_MISC_ECO_HW_CTL,
4881 bnx2_init_chip(struct bnx2 *bp)
4887 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4900 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4903 if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) &&
4904 (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0) &&
4905 !(bp->flags & BNX2_FLAG_PCIX))
4908 BNX2_WR(bp, BNX2_DMA_CONFIG, val);
4910 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
4911 val = BNX2_RD(bp, BNX2_TDMA_CONFIG);
4913 BNX2_WR(bp, BNX2_TDMA_CONFIG, val);
4916 if (bp->flags & BNX2_FLAG_PCIX) {
4919 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4921 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4925 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4932 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
4933 rc = bnx2_init_5709_context(bp);
4937 bnx2_init_context(bp);
4939 bnx2_init_cpus(bp);
4941 bnx2_init_nvram(bp);
4943 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4945 val = BNX2_RD(bp, BNX2_MQ_CONFIG);
4948 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
4950 if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)
4954 BNX2_WR(bp, BNX2_MQ_CONFIG, val);
4957 BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4958 BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4961 BNX2_WR(bp, BNX2_RV2P_CONFIG, val);
4964 val = BNX2_RD(bp, BNX2_TBDR_CONFIG);
4967 BNX2_WR(bp, BNX2_TBDR_CONFIG, val);
4969 val = bp->mac_addr[0] +
4970 (bp->mac_addr[1] << 8) +
4971 (bp->mac_addr[2] << 16) +
4972 bp->mac_addr[3] +
4973 (bp->mac_addr[4] << 8) +
4974 (bp->mac_addr[5] << 16);
4975 BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4978 mtu = bp->dev->mtu;
4982 BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4987 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4988 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4989 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4991 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
4993 bp->bnx2_napi[i].last_status_idx = 0;
4995 bp->idle_chk_status_idx = 0xffff;
4998 BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
5000 BNX2_WR(bp, BNX2_HC_STATUS_ADDR_L,
5001 (u64) bp->status_blk_mapping & 0xffffffff);
5002 BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
5004 BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
5005 (u64) bp->stats_blk_mapping & 0xffffffff);
5006 BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
5007 (u64) bp->stats_blk_mapping >> 32);
5009 BNX2_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
5010 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
5012 BNX2_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
5013 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
5015 BNX2_WR(bp, BNX2_HC_COMP_PROD_TRIP,
5016 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
5018 BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
5020 BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
5022 BNX2_WR(bp, BNX2_HC_COM_TICKS,
5023 (bp->com_ticks_int << 16) | bp->com_ticks);
5025 BNX2_WR(bp, BNX2_HC_CMD_TICKS,
5026 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
5028 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
5029 BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0);
5031 BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
5032 BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
5034 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)
5041 if (bp->flags & BNX2_FLAG_USING_MSIX) {
5042 BNX2_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
5048 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
5051 BNX2_WR(bp, BNX2_HC_CONFIG, val);
5053 if (bp->rx_ticks < 25)
5054 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1);
5056 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0);
5058 for (i = 1; i < bp->irq_nvecs; i++) {
5062 BNX2_WR(bp, base,
5067 BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
5068 (bp->tx_quick_cons_trip_int << 16) |
5069 bp->tx_quick_cons_trip);
5071 BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
5072 (bp->tx_ticks_int << 16) | bp->tx_ticks);
5074 BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
5075 (bp->rx_quick_cons_trip_int << 16) |
5076 bp->rx_quick_cons_trip);
5078 BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
5079 (bp->rx_ticks_int << 16) | bp->rx_ticks);
5083 BNX2_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
5085 BNX2_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
5088 bnx2_set_rx_mode(bp->dev);
5090 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
5091 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
5093 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
5095 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
5098 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
5099 BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
5103 bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND);
5109 bnx2_clear_ring_states(struct bnx2 *bp)
5117 bnapi = &bp->bnx2_napi[i];
5132 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
5137 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
5149 bnx2_ctx_wr(bp, cid_addr, offset0, val);
5152 bnx2_ctx_wr(bp, cid_addr, offset1, val);
5155 bnx2_ctx_wr(bp, cid_addr, offset2, val);
5158 bnx2_ctx_wr(bp, cid_addr, offset3, val);
5162 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
5169 bnapi = &bp->bnx2_napi[ring_num];
5177 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5190 bnx2_init_tx_context(bp, cid, txr);
5218 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5223 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5234 bp->rx_buf_use_size, bp->rx_max_ring);
5236 bnx2_init_rx_context(bp, cid);
5238 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
5239 val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5);
5240 BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5243 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
5244 if (bp->rx_pg_ring_size) {
5247 PAGE_SIZE, bp->rx_max_pg_ring);
5248 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
5249 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5250 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5254 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
5257 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
5259 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
5260 BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5264 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
5267 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
5270 for (i = 0; i < bp->rx_pg_ring_size; i++) {
5271 if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
5272 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
5273 ring_num, i, bp->rx_pg_ring_size);
5282 for (i = 0; i < bp->rx_ring_size; i++) {
5283 if (bnx2_alloc_rx_data(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
5284 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
5285 ring_num, i, bp->rx_ring_size);
5297 BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5298 BNX2_WR16(bp, rxr->rx_bidx_addr, prod);
5300 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
5304 bnx2_init_all_rings(struct bnx2 *bp)
5309 bnx2_clear_ring_states(bp);
5311 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5312 for (i = 0; i < bp->num_tx_rings; i++)
5313 bnx2_init_tx_ring(bp, i);
5315 if (bp->num_tx_rings > 1)
5316 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5319 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5320 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5322 for (i = 0; i < bp->num_rx_rings; i++)
5323 bnx2_init_rx_ring(bp, i);
5325 if (bp->num_rx_rings > 1) {
5331 tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift;
5333 BNX2_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);
5334 BNX2_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |
5345 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5370 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5375 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5380 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
5381 bp->rx_pg_ring_size = 0;
5382 bp->rx_max_pg_ring = 0;
5383 bp->rx_max_pg_ring_idx = 0;
5384 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
5385 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5391 bp->rx_pg_ring_size = jumbo_size;
5392 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5394 bp->rx_max_pg_ring_idx =
5395 (bp->rx_max_pg_ring * BNX2_RX_DESC_CNT) - 1;
5397 bp->rx_copy_thresh = 0;
5400 bp->rx_buf_use_size = rx_size;
5402 bp->rx_buf_size = kmalloc_size_roundup(
5403 SKB_DATA_ALIGN(bp->rx_buf_use_size + BNX2_RX_ALIGN) +
5405 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5406 bp->rx_ring_size = size;
5407 bp->rx_max_ring = bnx2_find_max_ring(size, BNX2_MAX_RX_RINGS);
5408 bp->rx_max_ring_idx = (bp->rx_max_ring * BNX2_RX_DESC_CNT) - 1;
5412 bnx2_free_tx_skbs(struct bnx2 *bp)
5416 for (i = 0; i < bp->num_tx_rings; i++) {
5417 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5434 dma_unmap_single(&bp->pdev->dev,
5445 dma_unmap_page(&bp->pdev->dev,
5452 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
5457 bnx2_free_rx_skbs(struct bnx2 *bp)
5461 for (i = 0; i < bp->num_rx_rings; i++) {
5462 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5469 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5476 dma_unmap_single(&bp->pdev->dev,
5478 bp->rx_buf_use_size,
5485 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5486 bnx2_free_rx_page(bp, rxr, j);
5491 bnx2_free_skbs(struct bnx2 *bp)
5493 bnx2_free_tx_skbs(bp);
5494 bnx2_free_rx_skbs(bp);
5498 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5502 rc = bnx2_reset_chip(bp, reset_code);
5503 bnx2_free_skbs(bp);
5507 if ((rc = bnx2_init_chip(bp)) != 0)
5510 bnx2_init_all_rings(bp);
5515 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5519 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5522 spin_lock_bh(&bp->phy_lock);
5523 bnx2_init_phy(bp, reset_phy);
5524 bnx2_set_link(bp);
5525 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5526 bnx2_remote_phy_event(bp);
5527 spin_unlock_bh(&bp->phy_lock);
5532 bnx2_shutdown_chip(struct bnx2 *bp)
5536 if (bp->flags & BNX2_FLAG_NO_WOL)
5538 else if (bp->wol)
5543 return bnx2_reset_chip(bp, reset_code);
5547 bnx2_test_registers(struct bnx2 *bp)
5668 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
5682 save_val = readl(bp->regview + offset);
5684 writel(0, bp->regview + offset);
5686 val = readl(bp->regview + offset);
5695 writel(0xffffffff, bp->regview + offset);
5697 val = readl(bp->regview + offset);
5706 writel(save_val, bp->regview + offset);
5710 writel(save_val, bp->regview + offset);
5718 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5729 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5731 if (bnx2_reg_rd_ind(bp, start + offset) !=
5741 bnx2_test_memory(struct bnx2 *bp)
5767 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
5773 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5786 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5798 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5807 bp->loopback = MAC_LOOPBACK;
5808 bnx2_set_mac_loopback(bp);
5811 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5814 bp->loopback = PHY_LOOPBACK;
5815 bnx2_set_phy_loopback(bp);
5820 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5821 skb = netdev_alloc_skb(bp->dev, pkt_size);
5825 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
5830 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
5832 if (dma_mapping_error(&bp->pdev->dev, map)) {
5837 BNX2_WR(bp, BNX2_HC_COMMAND,
5838 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5840 BNX2_RD(bp, BNX2_HC_COMMAND);
5858 BNX2_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5859 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5863 BNX2_WR(bp, BNX2_HC_COMMAND,
5864 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5866 BNX2_RD(bp, BNX2_HC_COMMAND);
5870 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE);
5887 dma_sync_single_for_cpu(&bp->pdev->dev,
5889 bp->rx_buf_use_size, DMA_FROM_DEVICE);
5914 bp->loopback = 0;
5924 bnx2_test_loopback(struct bnx2 *bp)
5928 if (!netif_running(bp->dev))
5931 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5932 spin_lock_bh(&bp->phy_lock);
5933 bnx2_init_phy(bp, 1);
5934 spin_unlock_bh(&bp->phy_lock);
5935 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5937 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5946 bnx2_test_nvram(struct bnx2 *bp)
5953 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5962 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5981 bnx2_test_link(struct bnx2 *bp)
5985 if (!netif_running(bp->dev))
5988 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5989 if (bp->link_up)
5993 spin_lock_bh(&bp->phy_lock);
5994 bnx2_enable_bmsr1(bp);
5995 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5996 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5997 bnx2_disable_bmsr1(bp);
5998 spin_unlock_bh(&bp->phy_lock);
6007 bnx2_test_intr(struct bnx2 *bp)
6012 if (!netif_running(bp->dev))
6015 status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
6018 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
6019 BNX2_RD(bp, BNX2_HC_COMMAND);
6022 if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
6038 bnx2_5706_serdes_has_link(struct bnx2 *bp)
6042 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
6045 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
6046 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
6051 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6052 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
6053 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
6058 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
6059 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
6060 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
6069 bnx2_5706_serdes_timer(struct bnx2 *bp)
6073 spin_lock(&bp->phy_lock);
6074 if (bp->serdes_an_pending) {
6075 bp->serdes_an_pending--;
6077 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6080 bp->current_interval = BNX2_TIMER_INTERVAL;
6082 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6085 if (bnx2_5706_serdes_has_link(bp)) {
6088 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
6089 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
6093 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
6094 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
6097 bnx2_write_phy(bp, 0x17, 0x0f01);
6098 bnx2_read_phy(bp, 0x15, &phy2);
6102 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6104 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
6106 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
6109 bp->current_interval = BNX2_TIMER_INTERVAL;
6114 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6115 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6116 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6118 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
6119 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
6120 bnx2_5706s_force_link_dn(bp, 1);
6121 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
6123 bnx2_set_link(bp);
6124 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6125 bnx2_set_link(bp);
6127 spin_unlock(&bp->phy_lock);
6131 bnx2_5708_serdes_timer(struct bnx2 *bp)
6133 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
6136 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
6137 bp->serdes_an_pending = 0;
6141 spin_lock(&bp->phy_lock);
6142 if (bp->serdes_an_pending)
6143 bp->serdes_an_pending--;
6144 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6147 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6149 bnx2_enable_forced_2g5(bp);
6150 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
6152 bnx2_disable_forced_2g5(bp);
6153 bp->serdes_an_pending = 2;
6154 bp->current_interval = BNX2_TIMER_INTERVAL;
6158 bp->current_interval = BNX2_TIMER_INTERVAL;
6160 spin_unlock(&bp->phy_lock);
6166 struct bnx2 *bp = from_timer(bp, t, timer);
6168 if (!netif_running(bp->dev))
6171 if (atomic_read(&bp->intr_sem) != 0)
6174 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6176 bnx2_chk_missed_msi(bp);
6178 bnx2_send_heart_beat(bp);
6180 bp->stats_blk->stat_FwRxDrop =
6181 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
6184 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
6185 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6188 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6189 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
6190 bnx2_5706_serdes_timer(bp);
6192 bnx2_5708_serdes_timer(bp);
6196 mod_timer(&bp->timer, jiffies + bp->current_interval);
6200 bnx2_request_irq(struct bnx2 *bp)
6206 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6211 for (i = 0; i < bp->irq_nvecs; i++) {
6212 irq = &bp->irq_tbl[i];
6214 &bp->bnx2_napi[i]);
6223 __bnx2_free_irq(struct bnx2 *bp)
6228 for (i = 0; i < bp->irq_nvecs; i++) {
6229 irq = &bp->irq_tbl[i];
6231 free_irq(irq->vector, &bp->bnx2_napi[i]);
6237 bnx2_free_irq(struct bnx2 *bp)
6240 __bnx2_free_irq(bp);
6241 if (bp->flags & BNX2_FLAG_USING_MSI)
6242 pci_disable_msi(bp->pdev);
6243 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6244 pci_disable_msix(bp->pdev);
6246 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
6250 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
6254 struct net_device *dev = bp->dev;
6255 const int len = sizeof(bp->irq_tbl[0].name);
6257 bnx2_setup_msix_tbl(bp);
6258 BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6259 BNX2_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6260 BNX2_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
6264 BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL);
6275 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent,
6284 bp->irq_nvecs = msix_vecs;
6285 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
6287 bp->irq_tbl[i].vector = msix_ent[i].vector;
6288 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6289 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6294 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6299 if (!bp->num_req_rx_rings)
6300 msix_vecs = max(cpus + 1, bp->num_req_tx_rings);
6301 else if (!bp->num_req_tx_rings)
6302 msix_vecs = max(cpus, bp->num_req_rx_rings);
6304 msix_vecs = max(bp->num_req_rx_rings, bp->num_req_tx_rings);
6308 bp->irq_tbl[0].handler = bnx2_interrupt;
6309 strcpy(bp->irq_tbl[0].name, bp->dev->name);
6310 bp->irq_nvecs = 1;
6311 bp->irq_tbl[0].vector = bp->pdev->irq;
6313 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
6314 bnx2_enable_msix(bp, msix_vecs);
6316 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6317 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6318 if (pci_enable_msi(bp->pdev) == 0) {
6319 bp->flags |= BNX2_FLAG_USING_MSI;
6320 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
6321 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6322 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6324 bp->irq_tbl[0].handler = bnx2_msi;
6326 bp->irq_tbl[0].vector = bp->pdev->irq;
6330 if (!bp->num_req_tx_rings)
6331 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
6333 bp->num_tx_rings = min(bp->irq_nvecs, bp->num_req_tx_rings);
6335 if (!bp->num_req_rx_rings)
6336 bp->num_rx_rings = bp->irq_nvecs;
6338 bp->num_rx_rings = min(bp->irq_nvecs, bp->num_req_rx_rings);
6340 netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings);
6342 return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings);
6349 struct bnx2 *bp = netdev_priv(dev);
6352 rc = bnx2_request_firmware(bp);
6358 bnx2_disable_int(bp);
6360 rc = bnx2_setup_int_mode(bp, disable_msi);
6363 bnx2_init_napi(bp);
6364 bnx2_napi_enable(bp);
6365 rc = bnx2_alloc_mem(bp);
6369 rc = bnx2_request_irq(bp);
6373 rc = bnx2_init_nic(bp, 1);
6377 mod_timer(&bp->timer, jiffies + bp->current_interval);
6379 atomic_set(&bp->intr_sem, 0);
6381 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
6383 bnx2_enable_int(bp);
6385 if (bp->flags & BNX2_FLAG_USING_MSI) {
6389 if (bnx2_test_intr(bp) != 0) {
6390 netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
6392 bnx2_disable_int(bp);
6393 bnx2_free_irq(bp);
6395 bnx2_setup_int_mode(bp, 1);
6397 rc = bnx2_init_nic(bp, 0);
6400 rc = bnx2_request_irq(bp);
6403 del_timer_sync(&bp->timer);
6406 bnx2_enable_int(bp);
6409 if (bp->flags & BNX2_FLAG_USING_MSI)
6411 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6419 bnx2_napi_disable(bp);
6420 bnx2_free_skbs(bp);
6421 bnx2_free_irq(bp);
6422 bnx2_free_mem(bp);
6423 bnx2_del_napi(bp);
6424 bnx2_release_firmware(bp);
6431 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
6436 if (!netif_running(bp->dev)) {
6441 bnx2_netif_stop(bp, true);
6443 pci_read_config_word(bp->pdev, PCI_COMMAND, &pcicmd);
6446 pci_restore_state(bp->pdev);
6447 pci_save_state(bp->pdev);
6449 rc = bnx2_init_nic(bp, 1);
6451 netdev_err(bp->dev, "failed to reset NIC, closing\n");
6452 bnx2_napi_enable(bp);
6453 dev_close(bp->dev);
6458 atomic_set(&bp->intr_sem, 1);
6459 bnx2_netif_start(bp, true);
6466 bnx2_dump_ftq(struct bnx2 *bp)
6470 struct net_device *dev = bp->dev;
6494 bnx2_reg_rd_ind(bp, ftq_arr[i].off));
6499 reg, bnx2_reg_rd_ind(bp, reg),
6500 bnx2_reg_rd_ind(bp, reg + 4),
6501 bnx2_reg_rd_ind(bp, reg + 8),
6502 bnx2_reg_rd_ind(bp, reg + 0x1c),
6503 bnx2_reg_rd_ind(bp, reg + 0x1c),
6504 bnx2_reg_rd_ind(bp, reg + 0x20));
6509 BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT);
6514 BNX2_WR(bp, BNX2_TBDC_BD_ADDR, i);
6515 BNX2_WR(bp, BNX2_TBDC_CAM_OPCODE,
6517 BNX2_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB);
6518 while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) &
6522 cid = BNX2_RD(bp, BNX2_TBDC_CID);
6523 bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX);
6524 valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE);
6533 bnx2_dump_state(struct bnx2 *bp)
6535 struct net_device *dev = bp->dev;
6538 pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);
6540 atomic_read(&bp->intr_sem), val1);
6541 pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);
6542 pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);
6545 BNX2_RD(bp, BNX2_EMAC_TX_STATUS),
6546 BNX2_RD(bp, BNX2_EMAC_RX_STATUS));
6548 BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
6550 BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
6551 if (bp->flags & BNX2_FLAG_USING_MSIX)
6553 BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
6559 struct bnx2 *bp = netdev_priv(dev);
6561 bnx2_dump_ftq(bp);
6562 bnx2_dump_state(bp);
6563 bnx2_dump_mcp_state(bp);
6566 schedule_work(&bp->reset_task);
6576 struct bnx2 *bp = netdev_priv(dev);
6589 bnapi = &bp->bnx2_napi[i];
6593 if (unlikely(bnx2_tx_avail(bp, txr) <
6648 mapping = dma_map_single(&bp->pdev->dev, skb->data, len,
6650 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
6678 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len,
6680 if (dma_mapping_error(&bp->pdev->dev, mapping))
6701 BNX2_WR16(bp, txr->tx_bidx_addr, prod);
6702 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6706 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6715 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6729 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
6737 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
6750 struct bnx2 *bp = netdev_priv(dev);
6752 bnx2_disable_int_sync(bp);
6753 bnx2_napi_disable(bp);
6755 del_timer_sync(&bp->timer);
6756 bnx2_shutdown_chip(bp);
6757 bnx2_free_irq(bp);
6758 bnx2_free_skbs(bp);
6759 bnx2_free_mem(bp);
6760 bnx2_del_napi(bp);
6761 bp->link_up = 0;
6762 netif_carrier_off(bp->dev);
6767 bnx2_save_stats(struct bnx2 *bp)
6769 u32 *hw_stats = (u32 *) bp->stats_blk;
6770 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
6794 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
6795 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
6798 (unsigned long) (bp->stats_blk->ctr + \
6799 bp->temp_stats_blk->ctr)
6804 struct bnx2 *bp = netdev_priv(dev);
6806 if (!bp->stats_blk)
6853 if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||
6854 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))
6879 struct bnx2 *bp = netdev_priv(dev);
6884 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6887 } else if (bp->phy_port == PORT_FIBRE)
6895 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6907 spin_lock_bh(&bp->phy_lock);
6908 cmd->base.port = bp->phy_port;
6909 advertising = bp->advertising;
6911 if (bp->autoneg & AUTONEG_SPEED) {
6918 cmd->base.speed = bp->line_speed;
6919 cmd->base.duplex = bp->duplex;
6920 if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES)) {
6921 if (bp->phy_flags & BNX2_PHY_FLAG_MDIX)
6931 spin_unlock_bh(&bp->phy_lock);
6933 cmd->base.phy_address = bp->phy_addr;
6947 struct bnx2 *bp = netdev_priv(dev);
6948 u8 autoneg = bp->autoneg;
6949 u8 req_duplex = bp->req_duplex;
6950 u16 req_line_speed = bp->req_line_speed;
6951 u32 advertising = bp->advertising;
6954 spin_lock_bh(&bp->phy_lock);
6959 if (cmd->base.port != bp->phy_port &&
6960 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6966 if (!netif_running(dev) && cmd->base.port != bp->phy_port)
6996 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
7007 bp->autoneg = autoneg;
7008 bp->advertising = advertising;
7009 bp->req_line_speed = req_line_speed;
7010 bp->req_duplex = req_duplex;
7017 err = bnx2_setup_phy(bp, cmd->base.port);
7020 spin_unlock_bh(&bp->phy_lock);
7028 struct bnx2 *bp = netdev_priv(dev);
7031 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
7032 strscpy(info->fw_version, bp->fw_version, sizeof(info->fw_version));
7048 struct bnx2 *bp = netdev_priv(dev);
7078 if (!netif_running(bp->dev))
7085 *p++ = BNX2_RD(bp, offset);
7098 struct bnx2 *bp = netdev_priv(dev);
7100 if (bp->flags & BNX2_FLAG_NO_WOL) {
7106 if (bp->wol)
7117 struct bnx2 *bp = netdev_priv(dev);
7123 if (bp->flags & BNX2_FLAG_NO_WOL)
7126 bp->wol = 1;
7129 bp->wol = 0;
7132 device_set_wakeup_enable(&bp->pdev->dev, bp->wol);
7140 struct bnx2 *bp = netdev_priv(dev);
7146 if (!(bp->autoneg & AUTONEG_SPEED)) {
7150 spin_lock_bh(&bp->phy_lock);
7152 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7155 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
7156 spin_unlock_bh(&bp->phy_lock);
7161 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7162 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
7163 spin_unlock_bh(&bp->phy_lock);
7167 spin_lock_bh(&bp->phy_lock);
7169 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
7170 bp->serdes_an_pending = 1;
7171 mod_timer(&bp->timer, jiffies + bp->current_interval);
7174 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
7176 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
7178 spin_unlock_bh(&bp->phy_lock);
7186 struct bnx2 *bp = netdev_priv(dev);
7188 return bp->link_up;
7194 struct bnx2 *bp = netdev_priv(dev);
7196 if (!bp->flash_info)
7199 return (int) bp->flash_size;
7206 struct bnx2 *bp = netdev_priv(dev);
7211 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
7220 struct bnx2 *bp = netdev_priv(dev);
7225 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
7235 struct bnx2 *bp = netdev_priv(dev);
7239 coal->rx_coalesce_usecs = bp->rx_ticks;
7240 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
7241 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
7242 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
7244 coal->tx_coalesce_usecs = bp->tx_ticks;
7245 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
7246 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
7247 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
7249 coal->stats_block_coalesce_usecs = bp->stats_ticks;
7259 struct bnx2 *bp = netdev_priv(dev);
7261 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7262 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7264 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
7265 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7267 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7268 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7270 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7271 if (bp->rx_quick_cons_trip_int > 0xff)
7272 bp->rx_quick_cons_trip_int = 0xff;
7274 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7275 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7277 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7278 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7280 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7281 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7283 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7284 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7287 bp->stats_ticks = coal->stats_block_coalesce_usecs;
7288 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
7289 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7290 bp->stats_ticks = USEC_PER_SEC;
7292 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7293 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7294 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7296 if (netif_running(bp->dev)) {
7297 bnx2_netif_stop(bp, true);
7298 bnx2_init_nic(bp, 0);
7299 bnx2_netif_start(bp, true);
7310 struct bnx2 *bp = netdev_priv(dev);
7315 ering->rx_pending = bp->rx_ring_size;
7316 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
7319 ering->tx_pending = bp->tx_ring_size;
7323 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx, bool reset_irq)
7325 if (netif_running(bp->dev)) {
7327 bnx2_save_stats(bp);
7329 bnx2_netif_stop(bp, true);
7330 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
7332 bnx2_free_irq(bp);
7333 bnx2_del_napi(bp);
7335 __bnx2_free_irq(bp);
7337 bnx2_free_skbs(bp);
7338 bnx2_free_mem(bp);
7341 bnx2_set_rx_ring_size(bp, rx);
7342 bp->tx_ring_size = tx;
7344 if (netif_running(bp->dev)) {
7348 rc = bnx2_setup_int_mode(bp, disable_msi);
7349 bnx2_init_napi(bp);
7353 rc = bnx2_alloc_mem(bp);
7356 rc = bnx2_request_irq(bp);
7359 rc = bnx2_init_nic(bp, 0);
7362 bnx2_napi_enable(bp);
7363 dev_close(bp->dev);
7367 mutex_lock(&bp->cnic_lock);
7369 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
7370 bnx2_setup_cnic_irq_info(bp);
7371 mutex_unlock(&bp->cnic_lock);
7373 bnx2_netif_start(bp, true);
7383 struct bnx2 *bp = netdev_priv(dev);
7392 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending,
7400 struct bnx2 *bp = netdev_priv(dev);
7402 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7403 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7404 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7410 struct bnx2 *bp = netdev_priv(dev);
7412 bp->req_flow_ctrl = 0;
7414 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7416 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7419 bp->autoneg |= AUTONEG_FLOW_CTRL;
7422 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7426 spin_lock_bh(&bp->phy_lock);
7427 bnx2_setup_phy(bp, bp->phy_port);
7428 spin_unlock_bh(&bp->phy_lock);
7588 struct bnx2 *bp = netdev_priv(dev);
7594 bnx2_netif_stop(bp, true);
7595 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7596 bnx2_free_skbs(bp);
7598 if (bnx2_test_registers(bp) != 0) {
7602 if (bnx2_test_memory(bp) != 0) {
7606 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
7609 if (!netif_running(bp->dev))
7610 bnx2_shutdown_chip(bp);
7612 bnx2_init_nic(bp, 1);
7613 bnx2_netif_start(bp, true);
7618 if (bp->link_up)
7624 if (bnx2_test_nvram(bp) != 0) {
7628 if (bnx2_test_intr(bp) != 0) {
7633 if (bnx2_test_link(bp) != 0) {
7659 struct bnx2 *bp = netdev_priv(dev);
7661 u32 *hw_stats = (u32 *) bp->stats_blk;
7662 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
7670 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||
7671 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) ||
7672 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A2) ||
7673 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))
7705 struct bnx2 *bp = netdev_priv(dev);
7709 bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG);
7710 BNX2_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7714 BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7723 BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7727 BNX2_WR(bp, BNX2_EMAC_LED, 0);
7728 BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save);
7738 struct bnx2 *bp = netdev_priv(dev);
7747 !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) &&
7749 bnx2_netif_stop(bp, false);
7752 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
7753 bnx2_netif_start(bp, false);
7763 struct bnx2 *bp = netdev_priv(dev);
7767 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {
7776 channels->rx_count = bp->num_rx_rings;
7777 channels->tx_count = bp->num_tx_rings;
7785 struct bnx2 *bp = netdev_priv(dev);
7790 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {
7798 bp->num_req_rx_rings = channels->rx_count;
7799 bp->num_req_tx_rings = channels->tx_count;
7802 rc = bnx2_change_ring_size(bp, bp->rx_ring_size,
7803 bp->tx_ring_size, true);
7846 struct bnx2 *bp = netdev_priv(dev);
7851 data->phy_id = bp->phy_addr;
7857 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7863 spin_lock_bh(&bp->phy_lock);
7864 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7865 spin_unlock_bh(&bp->phy_lock);
7873 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7879 spin_lock_bh(&bp->phy_lock);
7880 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7881 spin_unlock_bh(&bp->phy_lock);
7897 struct bnx2 *bp = netdev_priv(dev);
7904 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7913 struct bnx2 *bp = netdev_priv(dev);
7916 return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size,
7924 struct bnx2 *bp = netdev_priv(dev);
7927 for (i = 0; i < bp->irq_nvecs; i++) {
7928 struct bnx2_irq *irq = &bp->irq_tbl[i];
7931 irq->handler(irq->vector, &bp->bnx2_napi[i]);
7938 bnx2_get_5709_media(struct bnx2 *bp)
7940 u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7947 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7956 if (bp->func == 0) {
7961 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7969 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7976 bnx2_get_pci_speed(struct bnx2 *bp)
7980 reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS);
7984 bp->flags |= BNX2_FLAG_PCIX;
7986 clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7991 bp->bus_speed_mhz = 133;
7995 bp->bus_speed_mhz = 100;
8000 bp->bus_speed_mhz = 66;
8005 bp->bus_speed_mhz = 50;
8011 bp->bus_speed_mhz = 33;
8017 bp->bus_speed_mhz = 66;
8019 bp->bus_speed_mhz = 33;
8023 bp->flags |= BNX2_FLAG_PCI_32BIT;
8028 bnx2_read_vpd_fw_ver(struct bnx2 *bp)
8042 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data, BNX2_VPD_LEN);
8066 memcpy(bp->fw_version, &data[j], len);
8067 bp->fw_version[len] = ' ';
8076 struct bnx2 *bp;
8082 bp = netdev_priv(dev);
8084 bp->flags = 0;
8085 bp->phy_flags = 0;
8087 bp->temp_stats_blk =
8090 if (!bp->temp_stats_blk) {
8117 bp->pm_cap = pdev->pm_cap;
8118 if (bp->pm_cap == 0) {
8125 bp->dev = dev;
8126 bp->pdev = pdev;
8128 spin_lock_init(&bp->phy_lock);
8129 spin_lock_init(&bp->indirect_lock);
8131 mutex_init(&bp->cnic_lock);
8133 INIT_WORK(&bp->reset_task, bnx2_reset_task);
8135 bp->regview = pci_iomap(pdev, 0, MB_GET_CID_ADDR(TX_TSS_CID +
8137 if (!bp->regview) {
8147 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG,
8151 bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID);
8153 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
8159 bp->flags |= BNX2_FLAG_PCIE;
8160 if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)
8161 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
8163 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
8164 if (bp->pcix_cap == 0) {
8170 bp->flags |= BNX2_FLAG_BROKEN_STATS;
8173 if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&
8174 BNX2_CHIP_REV(bp) != BNX2_CHIP_REV_Ax) {
8176 bp->flags |= BNX2_FLAG_MSIX_CAP;
8179 if (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0 &&
8180 BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A1) {
8182 bp->flags |= BNX2_FLAG_MSI_CAP;
8186 if (BNX2_CHIP(bp) == BNX2_CHIP_5708)
8205 if (!(bp->flags & BNX2_FLAG_PCIE))
8206 bnx2_get_pci_speed(bp);
8209 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
8210 reg = BNX2_RD(bp, PCI_COMMAND);
8212 BNX2_WR(bp, PCI_COMMAND, reg);
8213 } else if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) &&
8214 !(bp->flags & BNX2_FLAG_PCIX)) {
8221 bnx2_init_nvram(bp);
8223 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
8225 if (bnx2_reg_rd_ind(bp, BNX2_MCP_TOE_ID) & BNX2_MCP_TOE_ID_FUNCTION_ID)
8226 bp->func = 1;
8230 u32 off = bp->func << 2;
8232 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
8234 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
8239 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
8248 bnx2_read_vpd_fw_ver(bp);
8250 j = strlen(bp->fw_version);
8251 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
8256 bp->fw_version[j++] = 'b';
8257 bp->fw_version[j++] = 'c';
8258 bp->fw_version[j++] = ' ';
8263 bp->fw_version[j++] = (num / k) + '0';
8268 bp->fw_version[j++] = '.';
8270 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
8272 bp->wol = 1;
8275 bp->flags |= BNX2_FLAG_ASF_ENABLE;
8278 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8284 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8288 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
8291 bp->fw_version[j++] = ' ';
8293 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
8295 memcpy(&bp->fw_version[j], ®, 4);
8300 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
8301 bp->mac_addr[0] = (u8) (reg >> 8);
8302 bp->mac_addr[1] = (u8) reg;
8304 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
8305 bp->mac_addr[2] = (u8) (reg >> 24);
8306 bp->mac_addr[3] = (u8) (reg >> 16);
8307 bp->mac_addr[4] = (u8) (reg >> 8);
8308 bp->mac_addr[5] = (u8) reg;
8310 bp->tx_ring_size = BNX2_MAX_TX_DESC_CNT;
8311 bnx2_set_rx_ring_size(bp, 255);
8313 bp->tx_quick_cons_trip_int = 2;
8314 bp->tx_quick_cons_trip = 20;
8315 bp->tx_ticks_int = 18;
8316 bp->tx_ticks = 80;
8318 bp->rx_quick_cons_trip_int = 2;
8319 bp->rx_quick_cons_trip = 12;
8320 bp->rx_ticks_int = 18;
8321 bp->rx_ticks = 18;
8323 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
8325 bp->current_interval = BNX2_TIMER_INTERVAL;
8327 bp->phy_addr = 1;
8335 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
8336 bnx2_get_5709_media(bp);
8337 else if (BNX2_CHIP_BOND(bp) & BNX2_CHIP_BOND_SERDES_BIT)
8338 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
8340 bp->phy_port = PORT_TP;
8341 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
8342 bp->phy_port = PORT_FIBRE;
8343 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
8345 bp->flags |= BNX2_FLAG_NO_WOL;
8346 bp->wol = 0;
8348 if (BNX2_CHIP(bp) == BNX2_CHIP_5706) {
8355 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
8357 bp->phy_addr = 2;
8359 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
8361 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5706 ||
8362 BNX2_CHIP(bp) == BNX2_CHIP_5708)
8363 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
8364 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&
8365 (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax ||
8366 BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Bx))
8367 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
8369 bnx2_init_fw_cap(bp);
8371 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||
8372 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||
8373 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1) ||
8374 !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
8375 bp->flags |= BNX2_FLAG_NO_WOL;
8376 bp->wol = 0;
8379 if (bp->flags & BNX2_FLAG_NO_WOL)
8380 device_set_wakeup_capable(&bp->pdev->dev, false);
8382 device_set_wakeup_enable(&bp->pdev->dev, bp->wol);
8384 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
8385 bp->tx_quick_cons_trip_int =
8386 bp->tx_quick_cons_trip;
8387 bp->tx_ticks_int = bp->tx_ticks;
8388 bp->rx_quick_cons_trip_int =
8389 bp->rx_quick_cons_trip;
8390 bp->rx_ticks_int = bp->rx_ticks;
8391 bp->comp_prod_trip_int = bp->comp_prod_trip;
8392 bp->com_ticks_int = bp->com_ticks;
8393 bp->cmd_ticks_int = bp->cmd_ticks;
8406 if (BNX2_CHIP(bp) == BNX2_CHIP_5706 && disable_msi == 0) {
8422 bnx2_set_default_link(bp);
8423 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8425 timer_setup(&bp->timer, bnx2_timer, 0);
8426 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
8429 if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN)
8430 bp->cnic_eth_dev.max_iscsi_conn =
8431 (bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) &
8433 bp->cnic_probe = bnx2_cnic_probe;
8440 pci_iounmap(pdev, bp->regview);
8441 bp->regview = NULL;
8450 kfree(bp->temp_stats_blk);
8456 bnx2_bus_string(struct bnx2 *bp, char *str)
8460 if (bp->flags & BNX2_FLAG_PCIE) {
8464 if (bp->flags & BNX2_FLAG_PCIX)
8466 if (bp->flags & BNX2_FLAG_PCI_32BIT)
8470 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8476 bnx2_del_napi(struct bnx2 *bp)
8480 for (i = 0; i < bp->irq_nvecs; i++)
8481 netif_napi_del(&bp->bnx2_napi[i].napi);
8485 bnx2_init_napi(struct bnx2 *bp)
8489 for (i = 0; i < bp->irq_nvecs; i++) {
8490 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8498 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll);
8499 bnapi->bp = bp;
8524 struct bnx2 *bp;
8529 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
8541 bp = netdev_priv(dev);
8552 bnx2_wait_dma_complete(bp);
8554 eth_hw_addr_set(dev, bp->mac_addr);
8560 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
8570 if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
8580 ((BNX2_CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8581 ((BNX2_CHIP_ID(bp) & 0x0ff0) >> 4),
8582 bnx2_bus_string(bp, str), (long)pci_resource_start(pdev, 0),
8588 pci_iounmap(pdev, bp->regview);
8601 struct bnx2 *bp = netdev_priv(dev);
8605 del_timer_sync(&bp->timer);
8606 cancel_work_sync(&bp->reset_task);
8608 pci_iounmap(bp->pdev, bp->regview);
8611 kfree(bp->temp_stats_blk);
8613 bnx2_release_firmware(bp);
8626 struct bnx2 *bp = netdev_priv(dev);
8629 cancel_work_sync(&bp->reset_task);
8630 bnx2_netif_stop(bp, true);
8632 del_timer_sync(&bp->timer);
8633 bnx2_shutdown_chip(bp);
8634 __bnx2_free_irq(bp);
8635 bnx2_free_skbs(bp);
8637 bnx2_setup_wol(bp);
8645 struct bnx2 *bp = netdev_priv(dev);
8650 bnx2_set_power_state(bp, PCI_D0);
8652 bnx2_request_irq(bp);
8653 bnx2_init_nic(bp, 1);
8654 bnx2_netif_start(bp, true);
8678 struct bnx2 *bp = netdev_priv(dev);
8689 bnx2_netif_stop(bp, true);
8690 del_timer_sync(&bp->timer);
8691 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8710 struct bnx2 *bp = netdev_priv(dev);
8724 err = bnx2_init_nic(bp, 1);
8731 bnx2_napi_enable(bp);
8749 struct bnx2 *bp = netdev_priv(dev);
8753 bnx2_netif_start(bp, true);
8762 struct bnx2 *bp;
8767 bp = netdev_priv(dev);
8768 if (!bp)
8773 dev_close(bp->dev);
8776 bnx2_set_power_state(bp, PCI_D3hot);