ethernet/broadcom/bnx2.c

544 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
1113 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1115 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1387 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1396 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1413 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1418 		bnx2_write_phy(bp, bp->mii_up1, up1);
1423 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1439 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1444 		bnx2_write_phy(bp, bp->mii_up1, up1);
1449 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1467 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1473 			bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1476 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1496 	bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1511 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1515 			bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1518 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1535 	bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1543 	bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1546 		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1548 		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1582 		bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1619 			bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1641         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1809 				bnx2_write_phy(bp, bp->mii_adv, adv &
1812 				bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1817 				bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1820 			bnx2_write_phy(bp, bp->mii_adv, adv);
1821 			bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1843 			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1849 		bnx2_write_phy(bp, bp->mii_adv, new_adv);
1850 		bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
2102 			bnx2_write_phy(bp, bp->mii_adv, new_adv);
2103 			bnx2_write_phy(bp, MII_CTRL1000, new_adv1000);
2104 			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
2119 		bnx2_write_phy(bp, bp->mii_adv, new_adv);
2136 			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
2145 		bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
2192 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2193 	bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2195 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2199 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2204 	bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2206 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2212 	bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2214 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2217 	bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2219 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2223 	bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2225 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2240 	bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2241 	bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2242 	bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2246 	bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2250 	bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2255 		bnx2_write_phy(bp, BCM5708S_UP1, val);
2262 		bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2266 		bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2267 		bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2278 			bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2280 			bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2281 			bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2303 		bnx2_write_phy(bp, 0x18, 0x7);
2305 		bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2307 		bnx2_write_phy(bp, 0x1c, 0x6c00);
2309 		bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2314 		bnx2_write_phy(bp, 0x18, 0x7);
2316 		bnx2_write_phy(bp, 0x18, val & ~0x4007);
2318 		bnx2_write_phy(bp, 0x1c, 0x6c00);
2320 		bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2335 		bnx2_write_phy(bp, 0x18, 0x0c00);
2336 		bnx2_write_phy(bp, 0x17, 0x000a);
2337 		bnx2_write_phy(bp, 0x15, 0x310b);
2338 		bnx2_write_phy(bp, 0x17, 0x201f);
2339 		bnx2_write_phy(bp, 0x15, 0x9506);
2340 		bnx2_write_phy(bp, 0x17, 0x401f);
2341 		bnx2_write_phy(bp, 0x15, 0x14e2);
2342 		bnx2_write_phy(bp, 0x18, 0x0400);
2346 		bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2350 		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2355 		bnx2_write_phy(bp, 0x18, 0x7);
2357 		bnx2_write_phy(bp, 0x18, val | 0x4000);
2360 		bnx2_write_phy(bp, 0x10, val | 0x1);
2363 		bnx2_write_phy(bp, 0x18, 0x7);
2365 		bnx2_write_phy(bp, 0x18, val & ~0x4007);
2368 		bnx2_write_phy(bp, 0x10, val & ~0x1);
2372 	bnx2_write_phy(bp, MII_BNX2_AUX_CTL, AUX_CTL_MISC_CTL);
2380 	bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val);
2453 	rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
6045 	bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
6051 	bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6058 	bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
6088 				bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
6097 		bnx2_write_phy(bp, 0x17, 0x0f01);
6104 			bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
6114 		bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
7162 		bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
7176 	bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
7880 		err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);