net/dsa/mt7530.c

92 core_write(struct mt7530_priv *priv, u32 reg, u32 val)
119 			 MII_MMD_DATA, val);
131 	u32 val;
155 	val = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
157 	val &= ~mask;
158 	val |= set;
161 			 MII_MMD_DATA, val);
170 core_set(struct mt7530_priv *priv, u32 reg, u32 val)
172 	core_rmw(priv, reg, 0, val);
176 core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
178 	core_rmw(priv, reg, val, 0);
182 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
186 	ret = regmap_write(priv->regmap, reg, val);
199 	u32 val;
201 	ret = regmap_read(priv->regmap, reg, &val);
209 	return val;
213 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
217 	mt7530_mii_write(priv, reg, val);
231 	u32 val;
235 	val = mt7530_mii_read(p->priv, p->reg);
239 	return val;
263 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
265 	mt7530_rmw(priv, reg, val, val);
269 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
271 	mt7530_rmw(priv, reg, val, 0);
277 	u32 val;
282 	val = ATC_BUSY | ATC_MAT(0) | cmd;
283 	mt7530_write(priv, MT7530_ATC, val);
286 	ret = readx_poll_timeout(_mt7530_read, &p, val,
287 				 !(val & ATC_BUSY), 20, 20000);
296 	val = mt7530_read(priv, MT7530_ATC);
297 	if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
301 		*rsp = val;
462 	u32 val;
464 	val = mt7530_read(priv, MT7531_CREV);
467 	if ((val & CHIP_REV_M) > 0)
475 	val = mt7530_read(priv, MT7531_PLLGP_EN);
476 	val &= ~EN_COREPLL;
477 	mt7530_write(priv, MT7531_PLLGP_EN, val);
480 	val = mt7530_read(priv, MT7531_PLLGP_EN);
481 	val |= SW_CLKSW;
482 	mt7530_write(priv, MT7531_PLLGP_EN, val);
484 	val = mt7530_read(priv, MT7531_PLLGP_CR0);
485 	val &= ~RG_COREPLL_EN;
486 	mt7530_write(priv, MT7531_PLLGP_CR0, val);
489 	val = mt7530_read(priv, MT7531_PLLGP_EN);
490 	val |= SW_PLLGP;
491 	mt7530_write(priv, MT7531_PLLGP_EN, val);
494 	val = mt7530_read(priv, MT7531_PLLGP_CR0);
495 	val &= ~RG_COREPLL_POSDIV_M;
496 	val |= 2 << RG_COREPLL_POSDIV_S;
497 	mt7530_write(priv, MT7531_PLLGP_CR0, val);
502 		val = mt7530_read(priv, MT7531_PLLGP_CR0);
503 		val &= ~RG_COREPLL_SDM_PCW_M;
504 		val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
505 		mt7530_write(priv, MT7531_PLLGP_CR0, val);
508 		val = mt7530_read(priv, MT7531_PLLGP_CR0);
509 		val &= ~RG_COREPLL_SDM_PCW_M;
510 		val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
511 		mt7530_write(priv, MT7531_PLLGP_CR0, val);
516 	val = mt7530_read(priv, MT7531_PLLGP_CR0);
517 	val |= RG_COREPLL_SDM_PCW_CHG;
518 	mt7530_write(priv, MT7531_PLLGP_CR0, val);
523 	val = mt7530_read(priv, MT7531_PLLGP_CR0);
524 	val &= ~RG_COREPLL_SDM_PCW_CHG;
525 	mt7530_write(priv, MT7531_PLLGP_CR0, val);
534 	val = mt7530_read(priv, MT7531_PLLGP_CR0);
535 	val |= RG_COREPLL_EN;
536 	mt7530_write(priv, MT7531_PLLGP_CR0, val);
538 	val = mt7530_read(priv, MT7531_PLLGP_EN);
539 	val |= EN_COREPLL;
540 	mt7530_write(priv, MT7531_PLLGP_EN, val);
559 				u16 val)
561 	return mdiobus_write_nested(priv->bus, port, regnum, val);
571 				int regnum, u16 val)
573 	return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val);
581 	u32 reg, val;
588 	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
589 				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
599 	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
600 				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
610 	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
611 				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
617 	ret = val & MT7531_MDIO_RW_DATA_MASK;
629 	u32 val, reg;
636 	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
637 				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
647 	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
648 				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
658 	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
659 				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
676 	u32 val;
682 	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
683 				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
689 	val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) |
692 	mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);
694 	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
695 				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
701 	ret = val & MT7531_MDIO_RW_DATA_MASK;
762 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val)
766 	return priv->info->phy_write_c22(priv, port, regnum, val);
771 		     u16 val)
775 	return priv->info->phy_write_c45(priv, port, devad, regnum, val);
877 	int val;
881 	val = mt7530_read(priv, MT753X_MTRAP);
883 	val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE;
888 		val |= MT7530_P5_PHY0_SEL;
899 		val |= MT7530_P5_MAC_SEL;
905 		val |= MT7530_P5_RGMII_MODE;
925 	mt7530_write(priv, MT753X_MTRAP, val);
927 	dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val,
1235 	u32 val;
1246 	val = mt7530_mii_read(priv, MT7530_GMACCR);
1247 	val &= ~MAX_RX_PKT_LEN_MASK;
1252 		val |= MAX_RX_PKT_LEN_1522;
1254 		val |= MAX_RX_PKT_LEN_1536;
1256 		val |= MAX_RX_PKT_LEN_1552;
1258 		val &= ~MAX_RX_JUMBO_MASK;
1259 		val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024));
1260 		val |= MAX_RX_PKT_LEN_JUMBO;
1263 	mt7530_mii_write(priv, MT7530_GMACCR, val);
1326 			   flags.val & BR_LEARNING ? 0 : SA_DIS);
1330 			   flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
1334 			   flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
1338 			   flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
1652 	u32 val;
1655 	val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
1656 	mt7530_write(priv, MT7530_VTCR, val);
1659 	ret = readx_poll_timeout(_mt7530_read, &p, val,
1660 				 !(val & VTCR_BUSY), 20, 20000);
1666 	val = mt7530_read(priv, MT7530_VTCR);
1667 	if (val & VTCR_INVALID) {
1703 	u32 val;
1710 	val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) |
1712 	mt7530_write(priv, MT7530_VAWD1, val);
1722 		val = MT7530_VLAN_EGRESS_STACK;
1724 		val = MT7530_VLAN_EGRESS_UNTAG;
1726 		val = MT7530_VLAN_EGRESS_TAG;
1729 		   ETAG_CTRL_P(entry->port, val));
1737 	u32 val;
1741 	val = mt7530_read(priv, MT7530_VAWD1);
1742 	if (!(val & VLAN_VALID)) {
1749 		val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1751 		mt7530_write(priv, MT7530_VAWD1, val);
1763 	u32 val;
1768 	val = mt7530_read(priv, MT7530_VAWD1);
1770 	entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1782 	u32 val;
1787 	val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) |
1789 	mt7530_write(priv, MT7530_VAWD1, val);
1879 	u32 val;
1885 	val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1888 	monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val);
1889 	if (val & MT753X_MIRROR_EN(priv->id) &&
1893 	val |= MT753X_MIRROR_EN(priv->id);
1894 	val &= ~MT753X_MIRROR_PORT_MASK(priv->id);
1895 	val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port);
1896 	mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
1898 	val = mt7530_read(priv, MT7530_PCR_P(port));
1900 		val |= PORT_RX_MIR;
1903 		val |= PORT_TX_MIR;
1906 	mt7530_write(priv, MT7530_PCR_P(port), val);
1915 	u32 val;
1917 	val = mt7530_read(priv, MT7530_PCR_P(port));
1919 		val &= ~PORT_RX_MIR;
1922 		val &= ~PORT_TX_MIR;
1925 	mt7530_write(priv, MT7530_PCR_P(port), val);
1928 		val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1929 		val &= ~MT753X_MIRROR_EN(priv->id);
1930 		mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
2051 	u32 val;
2055 	val = mt7530_mii_read(priv, MT7530_SYS_INT_STS);
2056 	mt7530_mii_write(priv, MT7530_SYS_INT_STS, val);
2060 		if (BIT(p) & val) {
2328 	u32 id, val;
2384 	ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
2398 	if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) {
2424 	if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
2591 	u32 val, id;
2609 	ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
2627 	val = mt7530_read(priv, MT7531_TOP_SIG_SR);
2628 	priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
2658 	val = mt7531_ind_c45_phy_read(priv,
2661 	val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE;
2662 	val &= ~MT7531_PHY_PLL_OFF;
2665 				 MDIO_MMD_VEND2, CORE_PLL_GROUP4, val);
2797 	u32 val;
2799 	val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
2800 	val |= GP_CLK_EN;
2801 	val &= ~GP_MODE_MASK;
2802 	val |= GP_MODE(MT7531_GP_MODE_RGMII);
2803 	val &= ~CLK_SKEW_IN_MASK;
2804 	val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG);
2805 	val &= ~CLK_SKEW_OUT_MASK;
2806 	val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG);
2807 	val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY;
2811 		val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY);
2814 			val |= TXCLK_NO_REVERSE;
2815 			val |= RXCLK_NO_DELAY;
2818 			val |= TXCLK_NO_REVERSE;
2821 			val |= RXCLK_NO_DELAY;
2830 	mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
3092 	int val = 0;
3110 		val = MT7530_CPU_EN |
3114 	mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val);