can/esd/esdacc.c

36 /*   Two bit wide command masks to mask or unmask a single core IRQ */
44 static void acc_resetmode_enter(struct acc_core *core)
46 	acc_set_bits(core, ACC_CORE_OF_CTRL_MODE,
50 	acc_resetmode_entered(core);
53 static void acc_resetmode_leave(struct acc_core *core)
55 	acc_clear_bits(core, ACC_CORE_OF_CTRL_MODE,
59 	acc_resetmode_entered(core);
62 static void acc_txq_put(struct acc_core *core, u32 acc_id, u8 acc_dlc,
65 	acc_write32_noswap(core, ACC_CORE_OF_TXFIFO_DATA_1,
67 	acc_write32_noswap(core, ACC_CORE_OF_TXFIFO_DATA_0,
69 	acc_write32(core, ACC_CORE_OF_TXFIFO_DLC, acc_dlc);
71 	acc_write32(core, ACC_CORE_OF_TXFIFO_ID, acc_id);
74 static u8 acc_tx_fifo_next(struct acc_core *core, u8 tx_fifo_idx)
77 	if (tx_fifo_idx >= core->tx_fifo_size)
163 		struct acc_core *core = &cores[u];
165 		core->bmfifo.messages = mem + (u + 1U) * ACC_CORE_DMABUF_SIZE;
166 		core->bmfifo.irq_cnt = ov->bmfifo.irq_cnt + (u + 1U);
173 	struct acc_core *core = priv->core;
182 		acc_resetmode_enter(core);
202 	acc_set_bits(core, ACC_CORE_OF_CTRL_MODE, ctrl_mode);
204 	acc_resetmode_leave(core);
208 	tx_fifo_status = acc_read32(core, ACC_CORE_OF_TXFIFO_STATUS);
209 	core->tx_fifo_head = tx_fifo_status & 0xff;
210 	core->tx_fifo_tail = (tx_fifo_status >> 8) & 0xff;
219 	struct acc_core *core = priv->core;
221 	acc_clear_bits(core, ACC_CORE_OF_CTRL_MODE,
230 	acc_resetmode_enter(core);
234 	acc_write32(core, ACC_CORE_OF_TX_ABORT_MASK, 0xffff);
237 	acc_clear_bits(core, ACC_CORE_OF_CTRL_MODE,
247 	struct acc_core *core = priv->core;
249 	u8 tx_fifo_head = core->tx_fifo_head;
257 	/* Access core->tx_fifo_tail only once because it may be changed
260 	fifo_usage = tx_fifo_head - core->tx_fifo_tail;
262 		fifo_usage += core->tx_fifo_size;
264 	if (fifo_usage >= core->tx_fifo_size - 1) {
265 		netdev_err(core->netdev,
271 	if (fifo_usage == core->tx_fifo_size - 2)
285 	can_put_echo_skb(skb, netdev, core->tx_fifo_head, 0);
287 	core->tx_fifo_head = acc_tx_fifo_next(core, tx_fifo_head);
289 	acc_txq_put(core, acc_id, acc_dlc, cf->data);
298 	u32 core_status = acc_read32(priv->core, ACC_CORE_OF_STATUS);
315 				acc_read32(priv->core, ACC_CORE_OF_TXFIFO_STATUS);
318 			if (hw_fifo_head != priv->core->tx_fifo_head ||
319 			    hw_fifo_head != priv->core->tx_fifo_tail) {
322 					    priv->core->tx_fifo_tail,
323 					    priv->core->tx_fifo_head,
327 		acc_resetmode_leave(priv->core);
374 		acc_write32(priv->core, ACC_CORE_OF_BRP, brp);
375 		acc_write32(priv->core, ACC_CORE_OF_BTR, btr);
391 		acc_write32(priv->core, ACC_CORE_OF_BRP, brp);
392 		acc_write32(priv->core, ACC_CORE_OF_BTR, btr);
400 static void handle_core_msg_rxtxdone(struct acc_core *core,
403 	struct acc_net_priv *priv = netdev_priv(core->netdev);
404 	struct net_device_stats *stats = &core->netdev->stats;
408 		u8 tx_fifo_tail = core->tx_fifo_tail;
410 		if (core->tx_fifo_head == tx_fifo_tail) {
411 			netdev_warn(core->netdev,
424 		stats->tx_bytes += can_get_echo_skb(core->netdev, tx_fifo_tail,
427 		core->tx_fifo_tail = acc_tx_fifo_next(core, tx_fifo_tail);
429 		netif_wake_queue(core->netdev);
434 		skb = alloc_can_skb(core->netdev, &cf);
461 static void handle_core_msg_txabort(struct acc_core *core,
464 	struct net_device_stats *stats = &core->netdev->stats;
465 	u8 tx_fifo_tail = core->tx_fifo_tail;
469 	while (tx_fifo_tail != core->tx_fifo_head && (abort_mask)) {
476 		can_free_echo_skb(core->netdev, tx_fifo_tail, NULL);
480 		tx_fifo_tail = acc_tx_fifo_next(core, tx_fifo_tail);
482 	core->tx_fifo_tail = tx_fifo_tail;
484 		netdev_warn(core->netdev, "Unhandled aborted messages\n");
486 	if (!acc_resetmode_entered(core))
487 		netif_wake_queue(core->netdev);
490 static void handle_core_msg_overrun(struct acc_core *core,
493 	struct acc_net_priv *priv = netdev_priv(core->netdev);
494 	struct net_device_stats *stats = &core->netdev->stats;
507 	skb = alloc_can_err_skb(core->netdev, &cf);
519 static void handle_core_msg_buserr(struct acc_core *core,
522 	struct acc_net_priv *priv = netdev_priv(core->netdev);
523 	struct net_device_stats *stats = &core->netdev->stats;
556 	skb = alloc_can_err_skb(core->netdev, &cf);
577 handle_core_msg_errstatechange(struct acc_core *core,
580 	struct acc_net_priv *priv = netdev_priv(core->netdev);
598 			netif_wake_queue(core->netdev);
602 	skb = alloc_can_err_skb(core->netdev, &cf);
616 		can_change_state(core->netdev, cf, tx_state, rx_state);
630 		acc_write32(core, ACC_CORE_OF_TX_ABORT_MASK, 0xffff);
631 		can_bus_off(core->netdev);
635 static void handle_core_interrupt(struct acc_core *core)
637 	u32 msg_fifo_head = core->bmfifo.local_irq_cnt & 0xff;
639 	while (core->bmfifo.msg_fifo_tail != msg_fifo_head) {
641 			&core->bmfifo.messages[core->bmfifo.msg_fifo_tail];
645 			handle_core_msg_rxtxdone(core, &msg->rxtxdone);
649 			handle_core_msg_txabort(core, &msg->txabort);
653 			handle_core_msg_overrun(core, &msg->overrun);
657 			handle_core_msg_buserr(core, &msg->buserr);
662 			handle_core_msg_errstatechange(core,
671 		core->bmfifo.msg_fifo_tail =
672 				(core->bmfifo.msg_fifo_tail + 1) & 0xff;
680  * @cores: array of core structures
685  * It examines for all cores (the overview module core and the CAN cores)
691  * ACC_OV_OF_BM_IRQ_MASK. This register has for each core a two bit command
700  * For each CAN core with a pending IRQ handle_core_interrupt() handles all
702  * index) is written to the CAN core to acknowledge its handling.
728 		struct acc_core *core = &cores[i];
730 		if (READ_ONCE(*core->bmfifo.irq_cnt) != core->bmfifo.local_irq_cnt) {
732 			core->bmfifo.local_irq_cnt = READ_ONCE(*core->bmfifo.irq_cnt);
740 	 * call handle_{ov|core}_interrupt and then acknowledge the
752 		struct acc_core *core = &cores[i];
755 			handle_core_interrupt(core);
756 			acc_write32(core, ACC_OV_OF_BM_IRQ_COUNTER,
757 				    core->bmfifo.local_irq_cnt);