Lines Matching defs:nfc
251 int (*set_cdev)(struct stm32_fmc2_nfc *nfc);
294 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
300 regmap_update_bits(nfc->regmap, FMC2_PCR,
310 regmap_write(nfc->regmap, FMC2_PMEM, pmem);
317 regmap_write(nfc->regmap, FMC2_PATT, patt);
322 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
344 regmap_update_bits(nfc->regmap, FMC2_PCR, pcr_mask, pcr);
349 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
354 if (nand->cs_used[chipnr] == nfc->cs_sel)
357 nfc->cs_sel = nand->cs_used[chipnr];
361 if (nfc->dma_tx_ch) {
363 dma_cfg.dst_addr = nfc->data_phys_addr[nfc->cs_sel];
365 dma_cfg.dst_maxburst = nfc->tx_dma_max_burst /
368 ret = dmaengine_slave_config(nfc->dma_tx_ch, &dma_cfg);
370 dev_err(nfc->dev, "tx DMA engine slave config failed\n");
375 if (nfc->dma_rx_ch) {
377 dma_cfg.src_addr = nfc->data_phys_addr[nfc->cs_sel];
379 dma_cfg.src_maxburst = nfc->rx_dma_max_burst /
382 ret = dmaengine_slave_config(nfc->dma_rx_ch, &dma_cfg);
384 dev_err(nfc->dev, "rx DMA engine slave config failed\n");
389 if (nfc->dma_ecc_ch) {
395 dma_cfg.src_addr = nfc->io_phys_addr;
400 ret = dmaengine_slave_config(nfc->dma_ecc_ch, &dma_cfg);
402 dev_err(nfc->dev, "ECC DMA engine slave config failed\n");
407 nfc->dma_ecc_len = chip->ecc.strength == FMC2_ECC_HAM ?
414 static void stm32_fmc2_nfc_set_buswidth_16(struct stm32_fmc2_nfc *nfc, bool set)
421 regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_PWID, pcr);
424 static void stm32_fmc2_nfc_set_ecc(struct stm32_fmc2_nfc *nfc, bool enable)
426 regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_ECCEN,
430 static void stm32_fmc2_nfc_enable_seq_irq(struct stm32_fmc2_nfc *nfc)
432 nfc->irq_state = FMC2_IRQ_SEQ;
434 regmap_update_bits(nfc->regmap, FMC2_CSQIER,
438 static void stm32_fmc2_nfc_disable_seq_irq(struct stm32_fmc2_nfc *nfc)
440 regmap_update_bits(nfc->regmap, FMC2_CSQIER, FMC2_CSQIER_TCIE, 0);
442 nfc->irq_state = FMC2_IRQ_UNKNOWN;
445 static void stm32_fmc2_nfc_clear_seq_irq(struct stm32_fmc2_nfc *nfc)
447 regmap_write(nfc->regmap, FMC2_CSQICR, FMC2_CSQICR_CLEAR_IRQ);
450 static void stm32_fmc2_nfc_enable_bch_irq(struct stm32_fmc2_nfc *nfc, int mode)
452 nfc->irq_state = FMC2_IRQ_BCH;
455 regmap_update_bits(nfc->regmap, FMC2_BCHIER,
458 regmap_update_bits(nfc->regmap, FMC2_BCHIER,
462 static void stm32_fmc2_nfc_disable_bch_irq(struct stm32_fmc2_nfc *nfc)
464 regmap_update_bits(nfc->regmap, FMC2_BCHIER,
467 nfc->irq_state = FMC2_IRQ_UNKNOWN;
470 static void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc)
472 regmap_write(nfc->regmap, FMC2_BCHICR, FMC2_BCHICR_CLEAR_IRQ);
481 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
483 stm32_fmc2_nfc_set_ecc(nfc, false);
486 regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_WEN,
489 reinit_completion(&nfc->complete);
490 stm32_fmc2_nfc_clear_bch_irq(nfc);
491 stm32_fmc2_nfc_enable_bch_irq(nfc, mode);
494 stm32_fmc2_nfc_set_ecc(nfc, true);
512 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
516 ret = regmap_read_poll_timeout(nfc->regmap, FMC2_SR, sr,
520 dev_err(nfc->dev, "ham timeout\n");
524 regmap_read(nfc->regmap, FMC2_HECCR, &heccr);
526 stm32_fmc2_nfc_set_ecc(nfc, false);
593 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
597 if (!wait_for_completion_timeout(&nfc->complete,
599 dev_err(nfc->dev, "bch timeout\n");
600 stm32_fmc2_nfc_disable_bch_irq(nfc);
605 regmap_read(nfc->regmap, FMC2_BCHPBR1, &bchpbr);
611 regmap_read(nfc->regmap, FMC2_BCHPBR2, &bchpbr);
619 regmap_read(nfc->regmap, FMC2_BCHPBR3, &bchpbr);
625 regmap_read(nfc->regmap, FMC2_BCHPBR4, &bchpbr);
629 stm32_fmc2_nfc_set_ecc(nfc, false);
676 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
680 if (!wait_for_completion_timeout(&nfc->complete,
682 dev_err(nfc->dev, "bch timeout\n");
683 stm32_fmc2_nfc_disable_bch_irq(nfc);
687 regmap_bulk_read(nfc->regmap, FMC2_BCHDSR0, ecc_sta, 5);
689 stm32_fmc2_nfc_set_ecc(nfc, false);
760 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
769 regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_WEN,
832 cfg[4] = FIELD_PREP(FMC2_CSQCAR2_NANDCEN, nfc->cs_sel);
844 regmap_bulk_write(nfc->regmap, FMC2_CSQCFGR1, cfg, 5);
856 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
859 struct dma_chan *dma_ch = nfc->dma_rx_ch;
872 dma_ch = nfc->dma_tx_ch;
875 for_each_sg(nfc->dma_data_sg.sgl, sg, eccsteps, s) {
880 ret = dma_map_sg(nfc->dev, nfc->dma_data_sg.sgl,
885 desc_data = dmaengine_prep_slave_sg(dma_ch, nfc->dma_data_sg.sgl,
893 reinit_completion(&nfc->dma_data_complete);
894 reinit_completion(&nfc->complete);
896 desc_data->callback_param = &nfc->dma_data_complete;
905 p = nfc->ecc_buf;
906 for_each_sg(nfc->dma_ecc_sg.sgl, sg, eccsteps, s) {
907 sg_set_buf(sg, p, nfc->dma_ecc_len);
908 p += nfc->dma_ecc_len;
911 ret = dma_map_sg(nfc->dev, nfc->dma_ecc_sg.sgl,
918 desc_ecc = dmaengine_prep_slave_sg(nfc->dma_ecc_ch,
919 nfc->dma_ecc_sg.sgl,
927 reinit_completion(&nfc->dma_ecc_complete);
929 desc_ecc->callback_param = &nfc->dma_ecc_complete;
934 dma_async_issue_pending(nfc->dma_ecc_ch);
937 stm32_fmc2_nfc_clear_seq_irq(nfc);
938 stm32_fmc2_nfc_enable_seq_irq(nfc);
941 regmap_update_bits(nfc->regmap, FMC2_CSQCR,
945 if (!wait_for_completion_timeout(&nfc->complete, timeout)) {
946 dev_err(nfc->dev, "seq timeout\n");
947 stm32_fmc2_nfc_disable_seq_irq(nfc);
950 dmaengine_terminate_all(nfc->dma_ecc_ch);
956 if (!wait_for_completion_timeout(&nfc->dma_data_complete, timeout)) {
957 dev_err(nfc->dev, "data DMA timeout\n");
964 if (!wait_for_completion_timeout(&nfc->dma_ecc_complete,
966 dev_err(nfc->dev, "ECC DMA timeout\n");
967 dmaengine_terminate_all(nfc->dma_ecc_ch);
974 dma_unmap_sg(nfc->dev, nfc->dma_ecc_sg.sgl,
978 dma_unmap_sg(nfc->dev, nfc->dma_data_sg.sgl, eccsteps, dma_data_dir);
1035 static u16 stm32_fmc2_nfc_get_mapping_status(struct stm32_fmc2_nfc *nfc)
1039 regmap_read(nfc->regmap, FMC2_CSQEMSR, &csqemsr);
1048 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1053 u32 *ecc_sta = (u32 *)nfc->ecc_buf;
1054 u16 sta_map = stm32_fmc2_nfc_get_mapping_status(nfc);
1107 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1125 sta_map = stm32_fmc2_nfc_get_mapping_status(nfc);
1181 struct stm32_fmc2_nfc *nfc = (struct stm32_fmc2_nfc *)dev_id;
1183 if (nfc->irq_state == FMC2_IRQ_SEQ)
1185 stm32_fmc2_nfc_disable_seq_irq(nfc);
1186 else if (nfc->irq_state == FMC2_IRQ_BCH)
1188 stm32_fmc2_nfc_disable_bch_irq(nfc);
1190 complete(&nfc->complete);
1198 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1199 void __iomem *io_addr_r = nfc->data_base[nfc->cs_sel];
1203 stm32_fmc2_nfc_set_buswidth_16(nfc, false);
1239 stm32_fmc2_nfc_set_buswidth_16(nfc, true);
1245 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1246 void __iomem *io_addr_w = nfc->data_base[nfc->cs_sel];
1250 stm32_fmc2_nfc_set_buswidth_16(nfc, false);
1286 stm32_fmc2_nfc_set_buswidth_16(nfc, true);
1292 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1297 if (regmap_read_poll_timeout(nfc->regmap, FMC2_SR, sr,
1300 dev_warn(nfc->dev, "Waitrdy timeout\n");
1307 regmap_write(nfc->regmap, FMC2_ICR, FMC2_ICR_CIHLF);
1310 return regmap_read_poll_timeout(nfc->regmap, FMC2_ISR, isr,
1319 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1337 nfc->cmd_base[nfc->cs_sel]);
1343 nfc->addr_base[nfc->cs_sel]);
1368 static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc)
1372 regmap_read(nfc->regmap, FMC2_PCR, &pcr);
1375 nfc->cs_sel = -1;
1403 if (nfc->dev == nfc->cdev)
1404 regmap_update_bits(nfc->regmap, FMC2_BCR1,
1407 regmap_write(nfc->regmap, FMC2_PCR, pcr);
1408 regmap_write(nfc->regmap, FMC2_PMEM, FMC2_PMEM_DEFAULT);
1409 regmap_write(nfc->regmap, FMC2_PATT, FMC2_PATT_DEFAULT);
1415 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1418 unsigned long hclk = clk_get_rate(nfc->clk);
1563 static int stm32_fmc2_nfc_dma_setup(struct stm32_fmc2_nfc *nfc)
1568 nfc->dma_tx_ch = dma_request_chan(nfc->dev, "tx");
1569 if (IS_ERR(nfc->dma_tx_ch)) {
1570 ret = PTR_ERR(nfc->dma_tx_ch);
1572 dev_err(nfc->dev,
1574 nfc->dma_tx_ch = NULL;
1578 ret = dma_get_slave_caps(nfc->dma_tx_ch, &caps);
1581 nfc->tx_dma_max_burst = caps.max_burst;
1583 nfc->dma_rx_ch = dma_request_chan(nfc->dev, "rx");
1584 if (IS_ERR(nfc->dma_rx_ch)) {
1585 ret = PTR_ERR(nfc->dma_rx_ch);
1587 dev_err(nfc->dev,
1589 nfc->dma_rx_ch = NULL;
1593 ret = dma_get_slave_caps(nfc->dma_rx_ch, &caps);
1596 nfc->rx_dma_max_burst = caps.max_burst;
1598 nfc->dma_ecc_ch = dma_request_chan(nfc->dev, "ecc");
1599 if (IS_ERR(nfc->dma_ecc_ch)) {
1600 ret = PTR_ERR(nfc->dma_ecc_ch);
1602 dev_err(nfc->dev,
1604 nfc->dma_ecc_ch = NULL;
1608 ret = sg_alloc_table(&nfc->dma_ecc_sg, FMC2_MAX_SG, GFP_KERNEL);
1613 nfc->ecc_buf = devm_kzalloc(nfc->dev, FMC2_MAX_ECC_BUF_LEN, GFP_KERNEL);
1614 if (!nfc->ecc_buf)
1617 ret = sg_alloc_table(&nfc->dma_data_sg, FMC2_MAX_SG, GFP_KERNEL);
1621 init_completion(&nfc->dma_data_complete);
1622 init_completion(&nfc->dma_ecc_complete);
1628 dev_warn(nfc->dev,
1638 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1644 if (nfc->dma_tx_ch && nfc->dma_rx_ch && nfc->dma_ecc_ch) {
1731 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1743 dev_err(nfc->dev,
1758 dev_err(nfc->dev, "no valid ECC settings set\n");
1763 dev_err(nfc->dev, "nand page size is not supported\n");
1797 static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc,
1800 struct stm32_fmc2_nand *nand = &nfc->nand;
1809 dev_err(nfc->dev, "invalid reg property size\n");
1816 dev_err(nfc->dev, "could not retrieve reg property: %d\n",
1821 if (cs >= nfc->data->max_ncs) {
1822 dev_err(nfc->dev, "invalid reg value: %d\n", cs);
1826 if (nfc->cs_assigned & BIT(cs)) {
1827 dev_err(nfc->dev, "cs already assigned: %d\n", cs);
1831 nfc->cs_assigned |= BIT(cs);
1835 nand->wp_gpio = devm_fwnode_gpiod_get(nfc->dev, of_fwnode_handle(dn),
1840 return dev_err_probe(nfc->dev, ret,
1851 static int stm32_fmc2_nfc_parse_dt(struct stm32_fmc2_nfc *nfc)
1853 struct device_node *dn = nfc->dev->of_node;
1859 dev_err(nfc->dev, "NAND chip not defined\n");
1864 dev_err(nfc->dev, "too many NAND chips defined\n");
1869 ret = stm32_fmc2_nfc_parse_child(nfc, child);
1879 static int stm32_fmc2_nfc_set_cdev(struct stm32_fmc2_nfc *nfc)
1881 struct device *dev = nfc->dev;
1888 if (of_device_is_compatible(dev->of_node, "st,stm32mp1-fmc2-nfc")) {
1890 nfc->cdev = dev->parent;
1901 nfc->cdev = dev;
1910 struct stm32_fmc2_nfc *nfc;
1919 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1920 if (!nfc)
1923 nfc->dev = dev;
1924 nand_controller_init(&nfc->base);
1925 nfc->base.ops = &stm32_fmc2_nfc_controller_ops;
1927 nfc->data = of_device_get_match_data(dev);
1928 if (!nfc->data)
1931 if (nfc->data->set_cdev) {
1932 ret = nfc->data->set_cdev(nfc);
1936 nfc->cdev = dev->parent;
1939 ret = stm32_fmc2_nfc_parse_dt(nfc);
1943 ret = of_address_to_resource(nfc->cdev->of_node, 0, &cres);
1947 nfc->io_phys_addr = cres.start;
1949 nfc->regmap = device_node_to_regmap(nfc->cdev->of_node);
1950 if (IS_ERR(nfc->regmap))
1951 return PTR_ERR(nfc->regmap);
1953 if (nfc->dev == nfc->cdev)
1956 for (chip_cs = 0, mem_region = start_region; chip_cs < nfc->data->max_ncs;
1958 if (!(nfc->cs_assigned & BIT(chip_cs)))
1961 nfc->data_base[chip_cs] = devm_platform_get_and_ioremap_resource(pdev,
1963 if (IS_ERR(nfc->data_base[chip_cs]))
1964 return PTR_ERR(nfc->data_base[chip_cs]);
1966 nfc->data_phys_addr[chip_cs] = res->start;
1968 nfc->cmd_base[chip_cs] = devm_platform_ioremap_resource(pdev, mem_region + 1);
1969 if (IS_ERR(nfc->cmd_base[chip_cs]))
1970 return PTR_ERR(nfc->cmd_base[chip_cs]);
1972 nfc->addr_base[chip_cs] = devm_platform_ioremap_resource(pdev, mem_region + 2);
1973 if (IS_ERR(nfc->addr_base[chip_cs]))
1974 return PTR_ERR(nfc->addr_base[chip_cs]);
1982 dev_name(dev), nfc);
1988 init_completion(&nfc->complete);
1990 nfc->clk = devm_clk_get_enabled(nfc->cdev, NULL);
1991 if (IS_ERR(nfc->clk)) {
1993 return PTR_ERR(nfc->clk);
2006 ret = stm32_fmc2_nfc_dma_setup(nfc);
2010 stm32_fmc2_nfc_init(nfc);
2012 nand = &nfc->nand;
2017 chip->controller = &nfc->base;
2032 platform_set_drvdata(pdev, nfc);
2043 if (nfc->dma_ecc_ch)
2044 dma_release_channel(nfc->dma_ecc_ch);
2045 if (nfc->dma_tx_ch)
2046 dma_release_channel(nfc->dma_tx_ch);
2047 if (nfc->dma_rx_ch)
2048 dma_release_channel(nfc->dma_rx_ch);
2050 sg_free_table(&nfc->dma_data_sg);
2051 sg_free_table(&nfc->dma_ecc_sg);
2058 struct stm32_fmc2_nfc *nfc = platform_get_drvdata(pdev);
2059 struct stm32_fmc2_nand *nand = &nfc->nand;
2067 if (nfc->dma_ecc_ch)
2068 dma_release_channel(nfc->dma_ecc_ch);
2069 if (nfc->dma_tx_ch)
2070 dma_release_channel(nfc->dma_tx_ch);
2071 if (nfc->dma_rx_ch)
2072 dma_release_channel(nfc->dma_rx_ch);
2074 sg_free_table(&nfc->dma_data_sg);
2075 sg_free_table(&nfc->dma_ecc_sg);
2082 struct stm32_fmc2_nfc *nfc = dev_get_drvdata(dev);
2083 struct stm32_fmc2_nand *nand = &nfc->nand;
2085 clk_disable_unprepare(nfc->clk);
2096 struct stm32_fmc2_nfc *nfc = dev_get_drvdata(dev);
2097 struct stm32_fmc2_nand *nand = &nfc->nand;
2102 ret = clk_prepare_enable(nfc->clk);
2108 stm32_fmc2_nfc_init(nfc);
2112 for (chip_cs = 0; chip_cs < nfc->data->max_ncs; chip_cs++) {
2113 if (!(nfc->cs_assigned & BIT(chip_cs)))
2140 .compatible = "st,stm32mp1-fmc2-nfc",
2144 .compatible = "st,stm32mp25-fmc2-nfc",