nand/raw/mtk_nand.c

216 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
218 	return nfc->buffer + i * mtk_data_len(chip);
223 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
225 	return nfc->buffer + i * mtk_data_len(chip) + chip->ecc.size;
228 static inline void nfi_writel(struct mtk_nfc *nfc, u32 val, u32 reg)
230 	writel(val, nfc->regs + reg);
233 static inline void nfi_writew(struct mtk_nfc *nfc, u16 val, u32 reg)
235 	writew(val, nfc->regs + reg);
238 static inline void nfi_writeb(struct mtk_nfc *nfc, u8 val, u32 reg)
240 	writeb(val, nfc->regs + reg);
243 static inline u32 nfi_readl(struct mtk_nfc *nfc, u32 reg)
245 	return readl_relaxed(nfc->regs + reg);
248 static inline u16 nfi_readw(struct mtk_nfc *nfc, u32 reg)
250 	return readw_relaxed(nfc->regs + reg);
253 static inline u8 nfi_readb(struct mtk_nfc *nfc, u32 reg)
255 	return readb_relaxed(nfc->regs + reg);
258 static void mtk_nfc_hw_reset(struct mtk_nfc *nfc)
260 	struct device *dev = nfc->dev;
265 	nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON);
268 	ret = readl_poll_timeout(nfc->regs + NFI_MASTER_STA, val,
276 	nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON);
277 	nfi_writew(nfc, STAR_DE, NFI_STRDATA);
280 static int mtk_nfc_send_command(struct mtk_nfc *nfc, u8 command)
282 	struct device *dev = nfc->dev;
286 	nfi_writel(nfc, command, NFI_CMD);
288 	ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val,
298 static int mtk_nfc_send_address(struct mtk_nfc *nfc, int addr)
300 	struct device *dev = nfc->dev;
304 	nfi_writel(nfc, addr, NFI_COLADDR);
305 	nfi_writel(nfc, 0, NFI_ROWADDR);
306 	nfi_writew(nfc, 1, NFI_ADDRNOB);
308 	ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val,
322 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
356 		dev_err(nfc->dev, "invalid page len: %d\n", mtd->writesize);
367 	for (i = 0; i < nfc->caps->num_spare_size; i++) {
368 		if (nfc->caps->spare_size[i] == spare)
372 	if (i == nfc->caps->num_spare_size) {
373 		dev_err(nfc->dev, "invalid spare size %d\n", spare);
377 	fmt |= i << nfc->caps->pageformat_spare_shift;
381 	nfi_writel(nfc, fmt, NFI_PAGEFMT);
383 	nfc->ecc_cfg.strength = chip->ecc.strength;
384 	nfc->ecc_cfg.len = chip->ecc.size + mtk_nand->fdm.ecc_size;
389 static inline void mtk_nfc_wait_ioready(struct mtk_nfc *nfc)
394 	rc = readb_poll_timeout_atomic(nfc->regs + NFI_PIO_DIRDY, val,
397 		dev_err(nfc->dev, "data not ready\n");
402 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
406 	reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK;
408 		reg = nfi_readw(nfc, NFI_CNFG);
410 		nfi_writew(nfc, reg, NFI_CNFG);
416 		reg = (nfc->caps->max_sector << CON_SEC_SHIFT) | CON_BRD;
417 		nfi_writel(nfc, reg, NFI_CON);
420 		nfi_writew(nfc, STAR_EN, NFI_STRDATA);
423 	mtk_nfc_wait_ioready(nfc);
425 	return nfi_readb(nfc, NFI_DATAR);
438 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
441 	reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK;
444 		reg = nfi_readw(nfc, NFI_CNFG) | CNFG_BYTE_RW;
445 		nfi_writew(nfc, reg, NFI_CNFG);
447 		reg = nfc->caps->max_sector << CON_SEC_SHIFT | CON_BWR;
448 		nfi_writel(nfc, reg, NFI_CON);
450 		nfi_writew(nfc, STAR_EN, NFI_STRDATA);
453 	mtk_nfc_wait_ioready(nfc);
454 	nfi_writeb(nfc, byte, NFI_DATAW);
468 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
474 		mtk_nfc_send_command(nfc, instr->ctx.cmd.opcode);
478 			mtk_nfc_send_address(nfc, instr->ctx.addr.addrs[i]);
489 		return readl_poll_timeout(nfc->regs + NFI_STA, status,
501 	struct mtk_nfc *nfc = nand_get_controller_data(nand);
506 	nfi_writel(nfc, mtk_nand->sels[cs], NFI_CSEL);
513 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
520 	mtk_nfc_hw_reset(nfc);
521 	nfi_writew(nfc, CNFG_OP_CUST, NFI_CNFG);
536 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
548 	rate = clk_get_rate(nfc->clk.nfi_clk);
550 	rate /= nfc->caps->nfi_clk_div;
617 	temp = nfi_readl(nfc, NFI_DEBUG_CON1);
620 	nfi_writel(nfc, temp, NFI_DEBUG_CON1);
636 	nfi_writel(nfc, trlt, NFI_ACCCON);
643 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
647 	nfc->ecc_cfg.mode = ECC_DMA_MODE;
648 	nfc->ecc_cfg.op = ECC_ENCODE;
650 	return mtk_ecc_encode(nfc->ecc, &nfc->ecc_cfg, data, size);
677 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
685 	memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize);
694 			mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1);
711 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
715 	memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize);
722 			mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1);
731 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
740 		vall = nfi_readl(nfc, NFI_FDML(i));
741 		valm = nfi_readl(nfc, NFI_FDMM(i));
750 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
769 		nfi_writel(nfc, vall, NFI_FDML(i));
770 		nfi_writel(nfc, valm, NFI_FDMM(i));
777 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
778 	struct device *dev = nfc->dev;
784 	ret = dma_mapping_error(nfc->dev, addr);
786 		dev_err(nfc->dev, "dma mapping error\n");
790 	reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AHB | CNFG_DMA_BURST_EN;
791 	nfi_writew(nfc, reg, NFI_CNFG);
793 	nfi_writel(nfc, chip->ecc.steps << CON_SEC_SHIFT, NFI_CON);
794 	nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR);
795 	nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN);
797 	init_completion(&nfc->done);
799 	reg = nfi_readl(nfc, NFI_CON) | CON_BWR;
800 	nfi_writel(nfc, reg, NFI_CON);
801 	nfi_writew(nfc, STAR_EN, NFI_STRDATA);
803 	ret = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500));
806 		nfi_writew(nfc, 0, NFI_INTR_EN);
811 	ret = readl_poll_timeout_atomic(nfc->regs + NFI_ADDRCNTR, reg,
819 	dma_unmap_single(nfc->dev, addr, len, DMA_TO_DEVICE);
820 	nfi_writel(nfc, 0, NFI_CON);
828 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
840 		reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AUTO_FMT_EN;
841 		nfi_writew(nfc, reg | CNFG_HW_ECC_EN, NFI_CNFG);
843 		nfc->ecc_cfg.op = ECC_ENCODE;
844 		nfc->ecc_cfg.mode = ECC_NFI_MODE;
845 		ret = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg);
848 			reg = nfi_readw(nfc, NFI_CNFG);
850 			nfi_writew(nfc, reg, NFI_CNFG);
855 		memcpy(nfc->buffer, buf, mtd->writesize);
856 		mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, raw);
857 		bufpoi = nfc->buffer;
869 		mtk_ecc_disable(nfc->ecc);
887 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
890 	return mtk_nfc_write_page(mtd, chip, nfc->buffer, pg, 1);
898 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
906 	return mtk_nfc_write_page(mtd, chip, nfc->buffer, page, 1);
918 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
924 	rc = nfi_readl(nfc, NFI_STA) & STA_EMP_PAGE;
932 	mtk_ecc_get_stats(nfc->ecc, &stats, sectors);
943 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
965 	addr = dma_map_single(nfc->dev, buf, len, DMA_FROM_DEVICE);
966 	rc = dma_mapping_error(nfc->dev, addr);
968 		dev_err(nfc->dev, "dma mapping error\n");
973 	reg = nfi_readw(nfc, NFI_CNFG);
977 		nfi_writew(nfc, reg, NFI_CNFG);
979 		nfc->ecc_cfg.mode = ECC_NFI_MODE;
980 		nfc->ecc_cfg.sectors = sectors;
981 		nfc->ecc_cfg.op = ECC_DECODE;
982 		rc = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg);
984 			dev_err(nfc->dev, "ecc enable\n");
988 			nfi_writew(nfc, reg, NFI_CNFG);
989 			dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE);
994 		nfi_writew(nfc, reg, NFI_CNFG);
997 	nfi_writel(nfc, sectors << CON_SEC_SHIFT, NFI_CON);
998 	nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN);
999 	nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR);
1001 	init_completion(&nfc->done);
1002 	reg = nfi_readl(nfc, NFI_CON) | CON_BRD;
1003 	nfi_writel(nfc, reg, NFI_CON);
1004 	nfi_writew(nfc, STAR_EN, NFI_STRDATA);
1006 	rc = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500));
1008 		dev_warn(nfc->dev, "read ahb/dma done timeout\n");
1010 	rc = readl_poll_timeout_atomic(nfc->regs + NFI_BYTELEN, reg,
1014 		dev_err(nfc->dev, "subpage done timeout\n");
1017 		rc = mtk_ecc_wait_done(nfc->ecc, ECC_DECODE);
1023 	dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE);
1028 	mtk_ecc_disable(nfc->ecc);
1033 	nfi_writel(nfc, 0, NFI_CON);
1058 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
1062 	memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize);
1063 	ret = mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, nfc->buffer,
1072 			mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1);
1087 static inline void mtk_nfc_hw_init(struct mtk_nfc *nfc)
1095 	nfi_writew(nfc, 0xf1, NFI_CNRNB);
1096 	nfi_writel(nfc, PAGEFMT_8K_16K, NFI_PAGEFMT);
1098 	mtk_nfc_hw_reset(nfc);
1100 	nfi_readl(nfc, NFI_INTR_STA);
1101 	nfi_writel(nfc, 0, NFI_INTR_EN);
1106 	struct mtk_nfc *nfc = id;
1109 	sta = nfi_readw(nfc, NFI_INTR_STA);
1110 	ien = nfi_readw(nfc, NFI_INTR_EN);
1115 	nfi_writew(nfc, ~sta & ien, NFI_INTR_EN);
1116 	complete(&nfc->done);
1166 	struct mtk_nfc *nfc = nand_get_controller_data(nand);
1170 				 mtk_ecc_get_parity_bits(nfc->ecc), 8);
1197 	struct mtk_nfc *nfc = nand_get_controller_data(nand);
1198 	const u8 *spare = nfc->caps->spare_size;
1210 	for (i = 0; i < nfc->caps->num_spare_size; i++) {
1231 	struct mtk_nfc *nfc = nand_get_controller_data(nand);
1253 			    nfc->caps->max_sector_size > 512) {
1268 		free = (nand->ecc.strength * mtk_ecc_get_parity_bits(nfc->ecc)
1280 					     mtk_ecc_get_parity_bits(nfc->ecc);
1284 					     mtk_ecc_get_parity_bits(nfc->ecc);
1288 	mtk_ecc_adjust_strength(nfc->ecc, &nand->ecc.strength);
1300 	struct mtk_nfc *nfc = nand_get_controller_data(chip);
1326 	nfc->buffer = devm_kzalloc(dev, len, GFP_KERNEL);
1327 	if (!nfc->buffer)
1339 static int mtk_nfc_nand_chip_init(struct device *dev, struct mtk_nfc *nfc,
1377 		if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1386 	nand->controller = &nfc->controller;
1389 	nand_set_controller_data(nand, nfc);
1414 	mtk_nfc_hw_init(nfc);
1427 	list_add_tail(&chip->node, &nfc->chips);
1432 static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
1439 		ret = mtk_nfc_nand_chip_init(dev, nfc, nand_np);
1478 		.compatible = "mediatek,mt2701-nfc",
1481 		.compatible = "mediatek,mt2712-nfc",
1484 		.compatible = "mediatek,mt7622-nfc",
1495 	struct mtk_nfc *nfc;
1498 	nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1499 	if (!nfc)
1502 	nand_controller_init(&nfc->controller);
1503 	INIT_LIST_HEAD(&nfc->chips);
1504 	nfc->controller.ops = &mtk_nfc_controller_ops;
1507 	nfc->ecc = of_mtk_ecc_get(np);
1508 	if (IS_ERR(nfc->ecc))
1509 		return PTR_ERR(nfc->ecc);
1510 	else if (!nfc->ecc)
1513 	nfc->caps = of_device_get_match_data(dev);
1514 	nfc->dev = dev;
1516 	nfc->regs = devm_platform_ioremap_resource(pdev, 0);
1517 	if (IS_ERR(nfc->regs)) {
1518 		ret = PTR_ERR(nfc->regs);
1522 	nfc->clk.nfi_clk = devm_clk_get_enabled(dev, "nfi_clk");
1523 	if (IS_ERR(nfc->clk.nfi_clk)) {
1525 		ret = PTR_ERR(nfc->clk.nfi_clk);
1529 	nfc->clk.pad_clk = devm_clk_get_enabled(dev, "pad_clk");
1530 	if (IS_ERR(nfc->clk.pad_clk)) {
1532 		ret = PTR_ERR(nfc->clk.pad_clk);
1542 	ret = devm_request_irq(dev, irq, mtk_nfc_irq, 0x0, "mtk-nand", nfc);
1554 	platform_set_drvdata(pdev, nfc);
1556 	ret = mtk_nfc_nand_chips_init(dev, nfc);
1565 	mtk_ecc_release(nfc->ecc);
1572 	struct mtk_nfc *nfc = platform_get_drvdata(pdev);
1577 	while (!list_empty(&nfc->chips)) {
1578 		mtk_chip = list_first_entry(&nfc->chips,
1587 	mtk_ecc_release(nfc->ecc);
1593 	struct mtk_nfc *nfc = dev_get_drvdata(dev);
1595 	clk_disable_unprepare(nfc->clk.nfi_clk);
1596 	clk_disable_unprepare(nfc->clk.pad_clk);
1603 	struct mtk_nfc *nfc = dev_get_drvdata(dev);
1611 	ret = clk_prepare_enable(nfc->clk.nfi_clk);
1617 	ret = clk_prepare_enable(nfc->clk.pad_clk);
1620 		clk_disable_unprepare(nfc->clk.nfi_clk);
1625 	list_for_each_entry(chip, &nfc->chips, node) {