nand/raw/lpc32xx_slc.c

167 	.ecc = lpc32xx_ooblayout_ecc,
405 static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count)
410 		uint32_t ce = ecc[i / 3];
529 	for (i = 0; i < chip->ecc.steps; i++) {
532 				       dma_buf + i * chip->ecc.size,
533 				       mtd->writesize / chip->ecc.steps, dir);
538 		if (i == chip->ecc.steps - 1)
570 	host->ecc_buf[chip->ecc.steps - 1] =
613 	status = lpc32xx_xfer(mtd, buf, chip->ecc.steps, 1);
619 	lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps);
628 	for (i = 0; i < chip->ecc.steps; i++) {
629 		stat = chip->ecc.correct(chip, buf, oobecc,
630 					 &tmpecc[i * chip->ecc.bytes]);
636 		buf += chip->ecc.size;
637 		oobecc += chip->ecc.bytes;
657 	chip->legacy.read_buf(chip, buf, chip->ecc.size * chip->ecc.steps);
680 	error = lpc32xx_xfer(mtd, (uint8_t *)buf, chip->ecc.steps, 0);
693 	lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps);
713 				chip->ecc.size * chip->ecc.steps);
774 	if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
788 	chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
790 	chip->ecc.size = 256;
791 	chip->ecc.strength = 1;
792 	chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES;
793 	chip->ecc.prepad = 0;
794 	chip->ecc.postpad = 0;
795 	chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome;
796 	chip->ecc.read_page = lpc32xx_nand_read_page_syndrome;
797 	chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome;
798 	chip->ecc.write_page = lpc32xx_nand_write_page_syndrome;
799 	chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome;
800 	chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome;
801 	chip->ecc.calculate = lpc32xx_nand_ecc_calculate;
802 	chip->ecc.correct = rawnand_sw_hamming_correct;
803 	chip->ecc.hwctl = lpc32xx_nand_ecc_enable;