raw/brcmnand/brcmnand.c

1434 		int ret;
1445 		ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY |
1449 		if (ret)
1456 		ret = bcmnand_ctrl_poll_status(host,
1464 		if (ret)
1682 	int ret;
1702 	ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0);
1703 	WARN_ON(ret);
1838 	int ret = 0;
1906 		ret = -EIO;
1917 		ret = -EIO;
1925 	if (!ret && edu_cmd == EDU_CMD_READ) {
1936 				ret = -EUCLEAN;
1938 			ret = -EBADMSG;
1941 	return ret;
2045 	int i, ret = 0;
2069 		if (ret != -EBADMSG) {
2073 				ret = -EBADMSG;
2076 		if (!ret) {
2080 				ret = -EUCLEAN;
2084 	return ret;
2108 	int ret;
2116 	ret = chip->ecc.read_page_raw(chip, buf, true, page);
2117 	if (ret)
2118 		return ret;
2126 		ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size,
2130 		if (ret < 0)
2131 			return ret;
2133 		bitflips = max(bitflips, ret);
2252 	int ret;
2258 	ret = brcmnand_read(mtd, chip, host->last_addr,
2261 	return ret;
2292 	int status, ret = 0;
2314 			ret = -EIO;
2348 			ret = -EIO;
2354 	return ret;
2377 	int ret = 0;
2381 	ret = brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
2384 	return ret;
2398 	int ret;
2401 	ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
2405 	return ret;
2415 	int ret = 0;
2453 		ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0);
2459 		ret = -EINVAL;
2463 	return ret;
2496 	int ret = 0;
2503 		ret = brcmnand_status(host);
2504 		if (ret < 0)
2505 			return ret;
2507 		*status = ret & 0xFF;
2511 		ret = brcmnand_reset(host);
2512 		if (ret < 0)
2513 			return ret;
2524 		ret = brcmnand_exec_instr(host, i, op);
2525 		if (ret)
2532 	return ret;
2685 	int ret;
2703 	ret = of_property_read_u32(np, "brcm,nand-oob-sector-size",
2705 	if (ret) {
2798 	ret = brcmnand_set_cfg(host, cfg);
2799 	if (ret)
2800 		return ret;
2829 	int ret;
2850 	ret = brcmstb_choose_ecc_layout(host);
2858 	return ret;
2873 	int ret;
2910 	ret = nand_scan(chip, 1);
2911 	if (ret)
2912 		return ret;
2914 	ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);
2915 	if (ret)
2918 	return ret;
3042 	int ret;
3064 			ret = devm_request_irq(dev, ctrl->edu_irq,
3067 			if (ret < 0) {
3069 					ctrl->edu_irq, ret);
3070 				return ret;
3089 	int ret;
3124 		ret = clk_prepare_enable(ctrl->clk);
3125 		if (ret)
3126 			return ret;
3128 		ret = PTR_ERR(ctrl->clk);
3129 		if (ret == -EPROBE_DEFER)
3130 			return ret;
3136 	ret = brcmnand_revision_init(ctrl);
3137 	if (ret)
3148 			ret = PTR_ERR(ctrl->nand_fc);
3161 			ret = PTR_ERR(ctrl->flash_dma_base);
3168 		ret = -EIO;
3170 			ret = dma_set_mask_and_coherent(&pdev->dev,
3172 		if (ret)
3173 			ret = dma_set_mask_and_coherent(&pdev->dev,
3175 		if (ret)
3187 			ret = -ENOMEM;
3194 			ret = -ENODEV;
3198 		ret = devm_request_irq(dev, ctrl->dma_irq,
3201 		if (ret < 0) {
3203 					ctrl->dma_irq, ret);
3211 		ret = brcmnand_edu_setup(pdev);
3212 		if (ret < 0)
3246 			ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
3254 			ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
3257 		if (ret < 0) {
3259 				ctrl->irq, ret);
3270 				ret = -ENOMEM;
3276 			ret = of_property_read_u32(child, "reg", &host->cs);
3277 			if (ret) {
3285 			ret = brcmnand_init_cs(host, NULL);
3286 			if (ret) {
3287 				if (ret == -EPROBE_DEFER) {
3303 		ret = -ENODEV;
3310 		ret = -ENOMEM;
3319 	ret = brcmnand_init_cs(host, pd->part_probe_types);
3320 	if (ret)
3327 		ret = -ENODEV;
3335 	return ret;
3345 	int ret;
3349 		ret = mtd_device_unregister(nand_to_mtd(chip));
3350 		WARN_ON(ret);