Lines Matching refs:nc
199 int (*remove)(struct atmel_nand_controller *nc);
200 void (*nand_init)(struct atmel_nand_controller *nc,
288 struct atmel_hsmc_nand_controller *nc = data;
292 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr);
294 rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
295 done = atmel_nfc_op_done(&nc->op, sr);
298 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd);
301 complete(&nc->complete);
306 static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
317 ret = regmap_read_poll_timeout(nc->base.smc,
319 atmel_nfc_op_done(&nc->op,
323 init_completion(&nc->complete);
324 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER,
325 nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
326 ret = wait_for_completion_timeout(&nc->complete,
333 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
336 if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
337 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
341 if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
342 dev_err(nc->base.dev, "Access to an undefined area\n");
346 if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
347 dev_err(nc->base.dev, "Access while busy\n");
351 if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
352 dev_err(nc->base.dev, "Wrong access size\n");
366 static int atmel_nand_dma_transfer(struct atmel_nand_controller *nc,
375 buf_dma = dma_map_single(nc->dev, buf, len, dir);
376 if (dma_mapping_error(nc->dev, dev_dma)) {
377 dev_err(nc->dev,
390 tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len,
393 dev_err(nc->dev, "Failed to prepare DMA memcpy\n");
402 dev_err(nc->dev, "Failed to do DMA tx_submit\n");
406 dma_async_issue_pending(nc->dmac);
408 dma_unmap_single(nc->dev, buf_dma, len, dir);
413 dma_unmap_single(nc->dev, buf_dma, len, dir);
416 dev_dbg(nc->dev, "Fall back to CPU I/O\n");
421 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
423 u8 *addrs = nc->op.addrs;
428 nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
430 for (i = 0; i < nc->op.ncmds; i++)
431 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
433 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
434 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
436 op |= ATMEL_NFC_CSID(nc->op.cs) |
437 ATMEL_NFC_ACYCLE(nc->op.naddrs);
439 if (nc->op.ncmds > 1)
445 if (nc->op.data != ATMEL_NFC_NO_DATA) {
447 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
449 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
454 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
457 regmap_write(nc->io, op, addr);
459 ret = atmel_nfc_wait(nc, poll, 0);
461 dev_err(nc->base.dev,
466 memset(&nc->op, 0, sizeof(nc->op));
474 struct atmel_nand_controller *nc;
476 nc = to_nand_controller(nand->base.controller);
483 if (nc->dmac && virt_addr_valid(buf) &&
485 !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,
498 struct atmel_nand_controller *nc;
500 nc = to_nand_controller(nand->base.controller);
507 if (nc->dmac && virt_addr_valid(buf) &&
509 !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,
531 struct atmel_hsmc_nand_controller *nc;
537 nc = to_hsmc_nand_controller(nand->base.controller);
539 return regmap_read_poll_timeout_atomic(nc->base.smc, ATMEL_HSMC_NFC_SR,
554 struct atmel_hsmc_nand_controller *nc;
560 nc = to_hsmc_nand_controller(nand->base.controller);
561 if (nc->cfg == cfg)
564 regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
570 nc->cfg = cfg;
576 struct atmel_nand_controller *nc;
579 nc = to_nand_controller(nand->base.controller);
583 nand->activecs->io.virt + nc->caps->cle_offs);
588 nand->activecs->io.virt + nc->caps->ale_offs);
636 struct atmel_hsmc_nand_controller *nc;
639 nc = to_hsmc_nand_controller(chip->controller);
641 nc->op.cs = nand->activecs->id;
646 nc->op.cmds[nc->op.ncmds++] = instr->ctx.cmd.opcode;
652 nc->op.addrs[nc->op.naddrs] = instr->ctx.addr.addrs[j];
653 nc->op.naddrs++;
657 return atmel_nfc_exec_op(nc, true);
721 struct atmel_hsmc_nand_controller *nc;
724 nc = to_hsmc_nand_controller(chip->controller);
726 if (nc->base.dmac)
727 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf,
728 nc->sram.dma, mtd->writesize,
733 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
736 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
744 struct atmel_hsmc_nand_controller *nc;
747 nc = to_hsmc_nand_controller(chip->controller);
749 if (nc->base.dmac)
750 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma,
755 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
758 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
765 struct atmel_hsmc_nand_controller *nc;
767 nc = to_hsmc_nand_controller(chip->controller);
770 nc->op.addrs[nc->op.naddrs++] = column;
776 nc->op.addrs[nc->op.naddrs++] = column >> 8;
780 nc->op.addrs[nc->op.naddrs++] = page;
781 nc->op.addrs[nc->op.naddrs++] = page >> 8;
784 nc->op.addrs[nc->op.naddrs++] = page >> 16;
791 struct atmel_nand_controller *nc;
794 nc = to_nand_controller(chip->controller);
801 dev_err(nc->dev,
819 struct atmel_nand_controller *nc;
824 nc = to_nand_controller(chip->controller);
831 dev_err(nc->dev,
854 struct atmel_nand_controller *nc;
859 nc = to_nand_controller(chip->controller);
866 dev_err(nc->dev,
988 struct atmel_hsmc_nand_controller *nc;
992 nc = to_hsmc_nand_controller(chip->controller);
996 nc->op.cmds[0] = NAND_CMD_SEQIN;
997 nc->op.ncmds = 1;
999 nc->op.cs = nand->activecs->id;
1000 nc->op.data = ATMEL_NFC_WRITE_DATA;
1006 ret = atmel_nfc_exec_op(nc, false);
1009 dev_err(nc->base.dev,
1049 struct atmel_hsmc_nand_controller *nc;
1053 nc = to_hsmc_nand_controller(chip->controller);
1064 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
1067 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
1070 nc->op.cs = nand->activecs->id;
1071 nc->op.data = ATMEL_NFC_READ_DATA;
1077 ret = atmel_nfc_exec_op(nc, false);
1080 dev_err(nc->base.dev,
1117 struct atmel_nand_controller *nc;
1120 nc = to_nand_controller(chip->controller);
1122 if (!nc->pmecc) {
1123 dev_err(nc->dev, "HW ECC not supported\n");
1127 if (nc->caps->legacy_of_bindings) {
1130 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap",
1134 if (!of_property_read_u32(nc->dev->of_node,
1167 nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1185 struct atmel_nand_controller *nc;
1188 nc = to_nand_controller(chip->controller);
1211 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1244 struct atmel_nand_controller *nc;
1247 nc = to_nand_controller(nand->base.controller);
1262 mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);
1473 struct atmel_nand_controller *nc;
1478 nc = to_nand_controller(nand->base.controller);
1489 atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1498 struct atmel_hsmc_nand_controller *nc;
1503 nc = to_hsmc_nand_controller(nand->base.controller);
1518 atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id,
1529 struct atmel_nand_controller *nc;
1535 nc = to_nand_controller(nand->base.controller);
1541 return nc->caps->ops->setup_interface(nand, csline, conf);
1549 struct atmel_nand_controller *nc;
1551 nc = to_nand_controller(nand->base.controller);
1553 return nc->caps->ops->exec_op(nand, op, check_only);
1556 static void atmel_nand_init(struct atmel_nand_controller *nc,
1562 mtd->dev.parent = nc->dev;
1563 nand->base.controller = &nc->base;
1565 if (!nc->mck || !nc->caps->ops->setup_interface)
1572 if (nc->dmac)
1576 if (nc->pmecc)
1580 static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1587 atmel_nand_init(nc, nand);
1622 static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1633 dev_err(nc->dev, "Missing or invalid reg property\n");
1637 nand = devm_kzalloc(nc->dev, struct_size(nand, cs, numcs), GFP_KERNEL);
1643 gpio = devm_fwnode_gpiod_get(nc->dev, of_fwnode_handle(np),
1646 dev_err(nc->dev,
1661 dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1669 dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1677 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res);
1688 gpio = devm_fwnode_gpiod_get_index(nc->dev,
1693 dev_err(nc->dev,
1705 gpio = devm_fwnode_gpiod_get_index(nc->dev,
1710 dev_err(nc->dev,
1726 atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1735 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1739 nc->caps->ops->nand_init(nc, nand);
1743 dev_err(nc->dev, "NAND scan failed: %d\n", ret);
1749 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret);
1754 list_add_tail(&nand->node, &nc->chips);
1760 atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1765 list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1775 atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc)
1777 struct device *dev = nc->dev;
1787 nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs),
1834 gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN);
1844 nand_set_flash_node(&nand->base, nc->dev->of_node);
1846 return atmel_nand_controller_add_nand(nc, nand);
1849 static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1852 struct device *dev = nc->dev;
1857 if (nc->caps->legacy_of_bindings)
1858 return atmel_nand_controller_legacy_add_nands(nc);
1881 nand = atmel_nand_create(nc, nand_np, reg_cells);
1887 ret = atmel_nand_controller_add_nand(nc, nand);
1895 atmel_nand_controller_remove_nands(nc);
1900 static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc)
1902 if (nc->dmac)
1903 dma_release_channel(nc->dmac);
1905 clk_put(nc->mck);
1979 struct atmel_nand_controller *nc = to_nand_controller(chip->controller);
1984 ret = nc->caps->ops->ecc_init(chip);
1988 if (nc->caps->legacy_of_bindings || !nc->dev->of_node) {
2006 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL,
2007 "%s:nand.%d", dev_name(nc->dev),
2010 dev_err(nc->dev, "Failed to allocate mtd->name\n");
2024 static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
2032 nand_controller_init(&nc->base);
2033 nc->base.ops = &atmel_nand_controller_ops;
2034 INIT_LIST_HEAD(&nc->chips);
2035 nc->dev = dev;
2036 nc->caps = caps;
2038 platform_set_drvdata(pdev, nc);
2040 nc->pmecc = devm_atmel_pmecc_get(dev);
2041 if (IS_ERR(nc->pmecc))
2042 return dev_err_probe(dev, PTR_ERR(nc->pmecc),
2045 if (nc->caps->has_dma && !atmel_nand_avoid_dma) {
2051 nc->dmac = dma_request_channel(mask, NULL, NULL);
2052 if (!nc->dmac)
2053 dev_err(nc->dev, "Failed to request DMA channel\n");
2057 if (nc->caps->legacy_of_bindings)
2060 nc->mck = of_clk_get(dev->parent->of_node, 0);
2061 if (IS_ERR(nc->mck)) {
2063 ret = PTR_ERR(nc->mck);
2074 nc->smc = syscon_node_to_regmap(np);
2076 if (IS_ERR(nc->smc)) {
2077 ret = PTR_ERR(nc->smc);
2085 if (nc->dmac)
2086 dma_release_channel(nc->dmac);
2092 atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
2094 struct device *dev = nc->base.dev;
2100 if (nc->base.caps->legacy_of_bindings)
2104 nc->base.caps->ebi_csa_regmap_name, 0);
2114 nc->ebi_csa_regmap = syscon_node_to_regmap(np);
2116 if (IS_ERR(nc->ebi_csa_regmap)) {
2117 ret = PTR_ERR(nc->ebi_csa_regmap);
2122 nc->ebi_csa = (struct atmel_smc_nand_ebi_csa_cfg *)match->data;
2130 nc->ebi_csa->offs += 4;
2136 atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc)
2144 struct device *dev = nc->base.dev;
2157 nc->clk = of_clk_get(nfc_np, 0);
2158 if (IS_ERR(nc->clk)) {
2159 ret = PTR_ERR(nc->clk);
2165 ret = clk_prepare_enable(nc->clk);
2172 nc->irq = of_irq_get(nand_np, 0);
2173 if (nc->irq <= 0) {
2174 ret = nc->irq ?: -ENXIO;
2196 nc->io = devm_regmap_init_mmio(dev, iomem, ®map_conf);
2197 if (IS_ERR(nc->io)) {
2198 ret = PTR_ERR(nc->io);
2219 nc->base.smc = devm_regmap_init_mmio(dev, iomem, ®map_conf);
2220 if (IS_ERR(nc->base.smc)) {
2221 ret = PTR_ERR(nc->base.smc);
2234 nc->sram.virt = devm_ioremap_resource(dev, &res);
2235 if (IS_ERR(nc->sram.virt)) {
2236 ret = PTR_ERR(nc->sram.virt);
2240 nc->sram.dma = res.start;
2249 atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
2251 struct device *dev = nc->base.dev;
2261 nc->hsmc_layout = atmel_hsmc_get_reg_layout(np);
2263 nc->irq = of_irq_get(np, 0);
2265 if (nc->irq <= 0) {
2266 ret = nc->irq ?: -ENXIO;
2279 nc->io = syscon_node_to_regmap(np);
2281 if (IS_ERR(nc->io)) {
2282 ret = PTR_ERR(nc->io);
2287 nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node,
2289 if (!nc->sram.pool) {
2290 dev_err(nc->base.dev, "Missing SRAM\n");
2294 nc->sram.virt = (void __iomem *)gen_pool_dma_alloc(nc->sram.pool,
2296 &nc->sram.dma);
2297 if (!nc->sram.virt) {
2298 dev_err(nc->base.dev,
2307 atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
2312 ret = atmel_nand_controller_remove_nands(nc);
2316 hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
2330 atmel_nand_controller_cleanup(nc);
2339 struct atmel_hsmc_nand_controller *nc;
2342 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2343 if (!nc)
2346 ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2351 ret = atmel_hsmc_nand_controller_legacy_init(nc);
2353 ret = atmel_hsmc_nand_controller_init(nc);
2359 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
2360 ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt,
2361 IRQF_SHARED, "nfc", nc);
2370 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
2372 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
2375 ret = atmel_nand_controller_add_nands(&nc->base);
2382 atmel_hsmc_nand_controller_remove(&nc->base);
2416 struct atmel_smc_nand_controller *nc;
2419 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2420 if (!nc)
2423 ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2427 ret = atmel_smc_nand_controller_init(nc);
2431 return atmel_nand_controller_add_nands(&nc->base);
2435 atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2439 ret = atmel_nand_controller_remove_nands(nc);
2443 atmel_nand_controller_cleanup(nc);
2630 struct atmel_nand_controller *nc = platform_get_drvdata(pdev);
2632 WARN_ON(nc->caps->ops->remove(nc));
2637 struct atmel_nand_controller *nc = dev_get_drvdata(dev);
2640 if (nc->pmecc)
2641 atmel_pmecc_reset(nc->pmecc);
2643 list_for_each_entry(nand, &nc->chips, node) {