Lines Matching refs:host
223 static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
229 sdhci_adma_write_desc(host, desc, addr, len, cmd);
235 sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
239 sdhci_adma_write_desc(host, desc, addr, len, cmd);
242 static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
244 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
247 return sdhci_pltfm_clk_get_max_clock(host);
252 static unsigned int rk35xx_get_max_clock(struct sdhci_host *host)
254 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
262 struct sdhci_host *host = mmc_priv(mmc);
267 * CMD23 argument on dwcmsch host controller.
270 host->flags &= ~SDHCI_AUTO_CMD23;
272 host->flags |= SDHCI_AUTO_CMD23;
282 static void dwcmshc_phy_1_8v_init(struct sdhci_host *host)
284 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
292 sdhci_writel(host, val, PHY_CNFG_R);
295 sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R);
298 sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R);
299 sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R);
302 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);
304 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);
311 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
312 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
313 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
317 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
323 sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
326 sdhci_writeb(host, FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK, PHY_DLLDL_CNFG_SLV_INPSEL),
330 sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R);
333 static void dwcmshc_phy_3_3v_init(struct sdhci_host *host)
335 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
343 sdhci_writel(host, val, PHY_CNFG_R);
346 sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R);
349 sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R);
350 sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R);
353 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);
355 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);
362 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
363 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
364 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
368 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
374 sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
377 sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R);
380 static void th1520_sdhci_set_phy(struct sdhci_host *host)
382 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
389 dwcmshc_phy_1_8v_init(host);
391 dwcmshc_phy_3_3v_init(host);
393 if ((host->mmc->caps2 & emmc_caps) == emmc_caps) {
394 emmc_ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
396 sdhci_writew(host, emmc_ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
399 sdhci_writeb(host, FIELD_PREP(PHY_DLL_CNFG1_SLVDLY_MASK, PHY_DLL_CNFG1_SLVDLY) |
403 static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
406 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
410 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
411 /* Select Bus Speed Mode for host */
428 ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
430 sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
437 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
440 static void th1520_set_uhs_signaling(struct sdhci_host *host,
443 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
446 dwcmshc_set_uhs_signaling(host, timing);
450 sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R);
451 th1520_sdhci_set_phy(host);
458 struct sdhci_host *host = mmc_priv(mmc);
459 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
463 vendor = sdhci_readl(host, reg);
469 sdhci_writel(host, vendor, reg);
475 struct sdhci_host *host = mmc_priv(mmc);
485 sdhci_reset(host, SDHCI_RESET_DATA);
490 static u32 dwcmshc_cqe_irq_handler(struct sdhci_host *host, u32 intmask)
495 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
498 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
505 struct sdhci_host *host = mmc_priv(mmc);
508 sdhci_writew(host, DWCMSHC_SDHCI_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
525 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
528 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
556 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock)
558 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
565 host->mmc->actual_clock = 0;
569 sdhci_set_clock(host, clock);
579 dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock);
581 sdhci_set_clock(host, clock);
585 extra = sdhci_readl(host, reg);
587 sdhci_writel(host, extra, reg);
594 sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL);
595 sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
596 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
597 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
606 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
611 sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL);
613 sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL);
622 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
628 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
629 err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,
633 dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n");
640 sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
642 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
643 host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
646 if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
654 sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
661 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
666 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
669 static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)
671 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
681 sdhci_reset(host, mask);
684 static int th1520_execute_tuning(struct sdhci_host *host, u32 opcode)
686 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
690 if (host->flags & SDHCI_HS400_TUNING)
693 sdhci_writeb(host, FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL),
695 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
722 sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
723 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
726 sdhci_start_tuning(host);
727 host->tuning_loop_count = 128;
728 host->tuning_err = __sdhci_execute_tuning(host, opcode);
729 if (host->tuning_err) {
732 sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
733 dev_err(mmc_dev(host->mmc), "tuning failed: %d\n", host->tuning_err);
736 sdhci_end_tuning(host);
741 static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask)
743 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
747 sdhci_reset(host, mask);
750 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
753 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758 static void cv18xx_sdhci_reset(struct sdhci_host *host, u8 mask)
760 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
764 sdhci_reset(host, mask);
766 if ((host->mmc->caps2 & emmc_caps) == emmc_caps) {
767 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
769 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
772 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
774 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
776 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG);
778 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG);
784 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY);
787 static void cv18xx_sdhci_set_tap(struct sdhci_host *host, int tap)
789 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
794 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
796 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
798 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
800 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
805 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY);
807 sdhci_writel(host, 0, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG);
810 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
828 static void cv18xx_sdhci_post_tuning(struct sdhci_host *host)
832 val = sdhci_readl(host, SDHCI_INT_STATUS);
834 sdhci_writel(host, val, SDHCI_INT_STATUS);
836 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
839 static int cv18xx_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
847 sdhci_reset_tuning(host);
852 cv18xx_sdhci_set_tap(host, min);
853 if (!cv18xx_retry_tuning(host->mmc, opcode, NULL))
861 cv18xx_sdhci_set_tap(host, max);
862 if (cv18xx_retry_tuning(host->mmc, opcode, NULL)) {
881 cv18xx_sdhci_post_tuning(host);
885 cv18xx_sdhci_set_tap(host, avg);
886 ret = mmc_send_tuning(host->mmc, opcode, NULL);
888 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
976 static void dwcmshc_cqhci_init(struct sdhci_host *host, struct platform_device *pdev)
979 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
985 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
988 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: not enough memory\n");
993 * For dwcmshc host controller we have to enable internal clock
996 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
998 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
999 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1001 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: internal clock enable error\n");
1005 cq_host->mmio = host->ioaddr + priv->vendor_specific_area2;
1009 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1011 dev_dbg(mmc_dev(host->mmc), "128-bit task descriptors\n");
1014 err = cqhci_init(cq_host, host->mmc, dma64);
1016 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: error %d\n", err);
1020 dev_dbg(mmc_dev(host->mmc), "CQE init done\n");
1025 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1027 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1033 host->mmc->caps2 &= ~(MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD);
1036 static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
1041 priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc));
1044 dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err);
1051 err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK35xx_MAX_CLKS,
1054 dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err);
1060 dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err);
1064 if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum",
1069 sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);
1071 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
1072 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
1077 static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
1083 if (host->mmc->f_max <= 52000000) {
1084 dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n",
1085 host->mmc->f_max);
1086 host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400);
1087 host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR);
1135 struct sdhci_host *host;
1148 host = sdhci_pltfm_init(pdev, pltfm_data,
1150 if (IS_ERR(host))
1151 return PTR_ERR(host);
1159 host->adma_table_cnt += extra;
1161 pltfm_host = sdhci_priv(host);
1180 err = mmc_of_parse(host->mmc);
1187 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK;
1189 host->mmc_host_ops.request = dwcmshc_request;
1190 host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe;
1191 host->mmc_host_ops.execute_tuning = dwcmshc_execute_tuning;
1207 err = dwcmshc_rk35xx_init(host, priv);
1229 host->flags &= ~SDHCI_SIGNALING_330;
1230 host->flags |= SDHCI_SIGNALING_180;
1233 sdhci_enable_v4_mode(host);
1238 sdhci_enable_v4_mode(host);
1241 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
1243 sdhci_enable_v4_mode(host);
1245 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1251 err = sdhci_setup_host(host);
1258 sdhci_readw(host, DWCMSHC_P_VENDOR_AREA2);
1260 dwcmshc_cqhci_init(host, pdev);
1264 dwcmshc_rk35xx_postinit(host, priv);
1266 err = __sdhci_add_host(host);
1275 sdhci_cleanup_host(host);
1290 static void dwcmshc_disable_card_clk(struct sdhci_host *host)
1294 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1297 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
1303 struct sdhci_host *host = platform_get_drvdata(pdev);
1304 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1312 sdhci_remove_host(host, 0);
1314 dwcmshc_disable_card_clk(host);
1327 struct sdhci_host *host = dev_get_drvdata(dev);
1328 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1335 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1336 ret = cqhci_suspend(host->mmc);
1341 ret = sdhci_suspend_host(host);
1358 struct sdhci_host *host = dev_get_drvdata(dev);
1359 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1381 ret = sdhci_resume_host(host);
1385 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1386 ret = cqhci_resume(host->mmc);
1408 static void dwcmshc_enable_card_clk(struct sdhci_host *host)
1412 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1415 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
1421 struct sdhci_host *host = dev_get_drvdata(dev);
1423 dwcmshc_disable_card_clk(host);
1430 struct sdhci_host *host = dev_get_drvdata(dev);
1432 dwcmshc_enable_card_clk(host);