mmc/host/sdhci-of-dwcmshc.c

286 	u32 val;
289 	val = PHY_CNFG_RSTN_DEASSERT;
290 	val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP);
291 	val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN);
292 	sdhci_writel(host, val, PHY_CNFG_R);
302 	val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);
303 	val &= ~(PHY_SDCLKDL_CNFG_UPDATE);
304 	sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);
307 	val = PHY_PAD_RXSEL_1V8;
308 	val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP);
309 	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
310 	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
311 	sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
312 	sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
313 	sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
315 	val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
316 	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
317 	sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
319 	val = PHY_PAD_RXSEL_1V8;
320 	val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN);
321 	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
322 	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
323 	sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
337 	u32 val;
340 	val = PHY_CNFG_RSTN_DEASSERT;
341 	val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP);
342 	val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN);
343 	sdhci_writel(host, val, PHY_CNFG_R);
353 	val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);
354 	val &= ~(PHY_SDCLKDL_CNFG_UPDATE);
355 	sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);
358 	val = PHY_PAD_RXSEL_3V3;
359 	val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP);
360 	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
361 	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
362 	sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
363 	sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
364 	sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
366 	val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
367 	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
368 	sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
370 	val = PHY_PAD_RXSEL_3V3;
371 	val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN);
372 	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
373 	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
374 	sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
688 	u32 val = 0;
695 	val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
705 	val &= ~(AT_CTRL_CI_SEL | AT_CTRL_RPT_TUNE_ERR | AT_CTRL_SW_TUNE_EN |
717 	val |= AT_CTRL_AT_EN | AT_CTRL_SWIN_TH_EN | AT_CTRL_TUNE_CLK_STOP_EN;
718 	val |= FIELD_PREP(AT_CTRL_PRE_CHANGE_DLY_MASK, AT_CTRL_PRE_CHANGE_DLY);
719 	val |= FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY);
720 	val |= FIELD_PREP(AT_CTRL_SWIN_TH_VAL_MASK, AT_CTRL_SWIN_TH_VAL);
722 	sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
723 	val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
731 		val &= ~AT_CTRL_AT_EN;
732 		sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
762 	u32 val, emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;
767 		val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
768 		val |= CV18XX_EMMC_FUNC_EN;
769 		sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
772 	val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
773 	val |= CV18XX_LATANCY_1T;
774 	sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
776 	val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG);
777 	val |= CV18XX_PHY_TX_BPS;
778 	sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG);
780 	val =  (FIELD_PREP(CV18XX_PHY_TX_DLY_MSK, 0) |
784 	sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY);
792 	u32 val;
798 	val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
799 	val &= ~CV18XX_LATANCY_1T;
800 	sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
802 	val =  (FIELD_PREP(CV18XX_PHY_TX_DLY_MSK, 0) |
805 	sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY);
830 	u32 val;
832 	val = sdhci_readl(host, SDHCI_INT_STATUS);
833 	val |= SDHCI_INT_DATA_AVAIL;
834 	sdhci_writel(host, val, SDHCI_INT_STATUS);