mmc/host/sdhci-of-dwcmshc.c

209 static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
215 		sdhci_adma_write_desc(host, desc, addr, len, cmd);
221 	sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
225 	sdhci_adma_write_desc(host, desc, addr, len, cmd);
228 static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
230 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
233 		return sdhci_pltfm_clk_get_max_clock(host);
238 static unsigned int rk35xx_get_max_clock(struct sdhci_host *host)
240 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
248 	struct sdhci_host *host = mmc_priv(mmc);
253 	 * CMD23 argument on dwcmsch host controller.
256 		host->flags &= ~SDHCI_AUTO_CMD23;
258 		host->flags |= SDHCI_AUTO_CMD23;
268 static void dwcmshc_phy_1_8v_init(struct sdhci_host *host)
270 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
278 	sdhci_writel(host, val, PHY_CNFG_R);
281 	sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R);
284 	sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R);
285 	sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R);
288 	val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);
290 	sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);
297 	sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
298 	sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
299 	sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
303 	sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
309 	sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
312 	sdhci_writeb(host, FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK, PHY_DLLDL_CNFG_SLV_INPSEL),
316 	sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R);
319 static void dwcmshc_phy_3_3v_init(struct sdhci_host *host)
321 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
329 	sdhci_writel(host, val, PHY_CNFG_R);
332 	sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R);
335 	sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R);
336 	sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R);
339 	val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);
341 	sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);
348 	sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
349 	sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
350 	sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
354 	sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
360 	sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
363 	sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R);
366 static void th1520_sdhci_set_phy(struct sdhci_host *host)
368 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
375 		dwcmshc_phy_1_8v_init(host);
377 		dwcmshc_phy_3_3v_init(host);
379 	if ((host->mmc->caps2 & emmc_caps) == emmc_caps) {
380 		emmc_ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
382 		sdhci_writew(host, emmc_ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
385 	sdhci_writeb(host, FIELD_PREP(PHY_DLL_CNFG1_SLVDLY_MASK, PHY_DLL_CNFG1_SLVDLY) |
389 static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
392 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
396 	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
397 	/* Select Bus Speed Mode for host */
414 		ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
416 		sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
423 	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
426 static void th1520_set_uhs_signaling(struct sdhci_host *host,
429 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
432 	dwcmshc_set_uhs_signaling(host, timing);
436 		sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R);
437 	th1520_sdhci_set_phy(host);
444 	struct sdhci_host *host = mmc_priv(mmc);
445 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
449 	vendor = sdhci_readl(host, reg);
455 	sdhci_writel(host, vendor, reg);
458 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock)
460 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
467 	host->mmc->actual_clock = 0;
471 		sdhci_set_clock(host, clock);
481 		dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock);
483 	sdhci_set_clock(host, clock);
487 	extra = sdhci_readl(host, reg);
489 	sdhci_writel(host, extra, reg);
496 		sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL);
497 		sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
498 		sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
499 		sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
508 		sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
513 	sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL);
515 	sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL);
524 	sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
530 	sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
531 	err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,
535 		dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n");
542 	sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
544 	if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
545 	    host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
548 	if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
556 		sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
563 	sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
568 	sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
571 static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)
573 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
583 	sdhci_reset(host, mask);
586 static int th1520_execute_tuning(struct sdhci_host *host, u32 opcode)
588 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
592 	if (host->flags & SDHCI_HS400_TUNING)
595 	sdhci_writeb(host, FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL),
597 	val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
624 	sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
625 	val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
628 	sdhci_start_tuning(host);
629 	host->tuning_loop_count = 128;
630 	host->tuning_err = __sdhci_execute_tuning(host, opcode);
631 	if (host->tuning_err) {
634 		sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
635 		dev_err(mmc_dev(host->mmc), "tuning failed: %d\n", host->tuning_err);
638 	sdhci_end_tuning(host);
643 static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask)
645 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
649 	sdhci_reset(host, mask);
652 		ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
655 			sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
660 static void cv18xx_sdhci_reset(struct sdhci_host *host, u8 mask)
662 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
666 	sdhci_reset(host, mask);
668 	if ((host->mmc->caps2 & emmc_caps) == emmc_caps) {
669 		val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
671 		sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
674 	val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
676 	sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
678 	val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG);
680 	sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG);
686 	sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY);
762 static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
767 	priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc));
770 		dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err);
777 	err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK35xx_MAX_CLKS,
780 		dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err);
786 		dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err);
790 	if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum",
795 	sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);
797 	sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
798 	sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
803 static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
809 	if (host->mmc->f_max <= 52000000) {
810 		dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n",
811 			 host->mmc->f_max);
812 		host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400);
813 		host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR);
861 	struct sdhci_host *host;
874 	host = sdhci_pltfm_init(pdev, pltfm_data,
876 	if (IS_ERR(host))
877 		return PTR_ERR(host);
885 	host->adma_table_cnt += extra;
887 	pltfm_host = sdhci_priv(host);
906 	err = mmc_of_parse(host->mmc);
913 		sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK;
915 	host->mmc_host_ops.request = dwcmshc_request;
916 	host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe;
932 		err = dwcmshc_rk35xx_init(host, priv);
954 			host->flags &= ~SDHCI_SIGNALING_330;
955 			host->flags |=  SDHCI_SIGNALING_180;
958 		sdhci_enable_v4_mode(host);
963 		sdhci_enable_v4_mode(host);
966 	host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
972 	err = sdhci_setup_host(host);
977 		dwcmshc_rk35xx_postinit(host, priv);
979 	err = __sdhci_add_host(host);
988 	sdhci_cleanup_host(host);
1003 static void dwcmshc_disable_card_clk(struct sdhci_host *host)
1007 	ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1010 		sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
1016 	struct sdhci_host *host = platform_get_drvdata(pdev);
1017 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1025 	sdhci_remove_host(host, 0);
1027 	dwcmshc_disable_card_clk(host);
1040 	struct sdhci_host *host = dev_get_drvdata(dev);
1041 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1048 	ret = sdhci_suspend_host(host);
1065 	struct sdhci_host *host = dev_get_drvdata(dev);
1066 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1088 	ret = sdhci_resume_host(host);
1109 static void dwcmshc_enable_card_clk(struct sdhci_host *host)
1113 	ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1116 		sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
1122 	struct sdhci_host *host = dev_get_drvdata(dev);
1124 	dwcmshc_disable_card_clk(host);
1131 	struct sdhci_host *host = dev_get_drvdata(dev);
1133 	dwcmshc_enable_card_clk(host);