Lines Matching defs:host
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
140 #define msm_host_readl(msm_host, host, offset) \
141 msm_host->var_ops->msm_readl_relaxed(host, offset)
143 #define msm_host_writel(msm_host, val, host, offset) \
144 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
243 u32 (*msm_readl_relaxed)(struct sdhci_host *host, u32 offset);
244 void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host,
295 static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host)
297 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
307 static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host,
310 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
316 static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host,
319 return readl_relaxed(host->ioaddr + offset);
323 struct sdhci_host *host, u32 offset)
325 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
332 struct sdhci_host *host, u32 offset)
334 writel_relaxed(val, host->ioaddr + offset);
337 static unsigned int msm_get_clock_mult_for_bus_mode(struct sdhci_host *host)
339 struct mmc_ios ios = host->mmc->ios;
349 host->flags & SDHCI_HS400_TUNING)
354 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
357 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
359 struct mmc_ios curr_ios = host->mmc->ios;
366 mult = msm_get_clock_mult_for_bus_mode(host);
368 rc = dev_pm_opp_set_rate(mmc_dev(host->mmc), desired_rate);
371 mmc_hostname(host->mmc), desired_rate, curr_ios.timing);
383 mmc_hostname(host->mmc), desired_rate, achieved_rate);
384 host->mmc->actual_clock = achieved_rate / mult;
390 mmc_hostname(host->mmc), achieved_rate, curr_ios.timing);
394 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
398 struct mmc_host *mmc = host->mmc;
400 sdhci_priv_msm_offset(host);
403 ck_out_en = !!(readl_relaxed(host->ioaddr +
414 ck_out_en = !!(readl_relaxed(host->ioaddr +
421 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
430 struct mmc_host *mmc = host->mmc;
432 sdhci_priv_msm_offset(host);
437 spin_lock_irqsave(&host->lock, flags);
439 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
442 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
445 rc = msm_dll_poll_ck_out_en(host, 0);
453 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
456 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
458 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
460 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
463 rc = msm_dll_poll_ck_out_en(host, 1);
467 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
470 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
477 spin_unlock_irqrestore(&host->lock, flags);
491 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
500 struct mmc_host *mmc = host->mmc;
593 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
597 sdhci_priv_msm_offset(host);
600 if (host->clock <= 112000000)
602 else if (host->clock <= 125000000)
604 else if (host->clock <= 137000000)
606 else if (host->clock <= 150000000)
608 else if (host->clock <= 162000000)
610 else if (host->clock <= 175000000)
612 else if (host->clock <= 187000000)
614 else if (host->clock <= 200000000)
617 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
620 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
624 static int msm_init_cm_dll(struct sdhci_host *host)
626 struct mmc_host *mmc = host->mmc;
627 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
638 spin_lock_irqsave(&host->lock, flags);
645 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
647 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
651 host->ioaddr + msm_offset->core_dll_config);
654 config = readl_relaxed(host->ioaddr +
657 writel_relaxed(config, host->ioaddr +
660 config = readl_relaxed(host->ioaddr +
663 writel_relaxed(config, host->ioaddr +
667 config = readl_relaxed(host->ioaddr +
670 writel_relaxed(config, host->ioaddr +
673 config = readl_relaxed(host->ioaddr +
676 writel_relaxed(config, host->ioaddr +
680 msm_cm_dll_set_freq(host);
686 config = readl_relaxed(host->ioaddr +
690 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
693 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
696 config = readl_relaxed(host->ioaddr +
701 writel_relaxed(config, host->ioaddr +
707 config = readl_relaxed(host->ioaddr +
710 writel_relaxed(config, host->ioaddr +
713 config = readl_relaxed(host->ioaddr +
716 writel_relaxed(config, host->ioaddr +
721 msm_cm_dll_set_freq(host);
722 config = readl_relaxed(host->ioaddr +
725 writel_relaxed(config, host->ioaddr +
736 writel_relaxed(config, host->ioaddr +
739 config = readl_relaxed(host->ioaddr +
746 writel_relaxed(config, host->ioaddr +
750 config = readl_relaxed(host->ioaddr +
753 writel_relaxed(config, host->ioaddr +
756 config = readl_relaxed(host->ioaddr +
759 writel_relaxed(config, host->ioaddr +
763 while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) &
769 spin_unlock_irqrestore(&host->lock, flags);
775 spin_unlock_irqrestore(&host->lock, flags);
779 static void msm_hc_select_default(struct sdhci_host *host)
781 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
788 config = readl_relaxed(host->ioaddr +
791 writel_relaxed(config, host->ioaddr +
795 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
798 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
807 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
810 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
819 static void msm_hc_select_hs400(struct sdhci_host *host)
821 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
823 struct mmc_ios ios = host->mmc->ios;
830 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
834 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
841 config = readl_relaxed(host->ioaddr +
845 writel_relaxed(config, host->ioaddr +
854 rc = readl_relaxed_poll_timeout(host->ioaddr +
863 mmc_hostname(host->mmc), dll_lock);
890 static void sdhci_msm_hc_select_mode(struct sdhci_host *host)
892 struct mmc_ios ios = host->mmc->ios;
895 host->flags & SDHCI_HS400_TUNING)
896 msm_hc_select_hs400(host);
898 msm_hc_select_default(host);
901 static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
903 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
910 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
916 ret = msm_init_cm_dll(host);
921 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
925 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
927 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
929 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
931 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
933 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
935 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
937 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
939 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
941 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
943 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
947 writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
948 writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
949 writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
950 writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
951 writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
952 writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
953 writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
954 writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
955 writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
959 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
961 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
963 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
965 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
967 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
969 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
971 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
973 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
975 ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
982 mmc_hostname(host->mmc), __func__);
986 ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
990 mmc_hostname(host->mmc), __func__, ret);
995 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
997 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
999 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1004 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
1006 struct mmc_host *mmc = host->mmc;
1009 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1012 sdhci_priv_msm_offset(host);
1014 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
1027 writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset);
1030 config = readl_relaxed(host->ioaddr +
1033 writel_relaxed(config, host->ioaddr +
1037 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2);
1039 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2);
1041 ret = readl_relaxed_poll_timeout(host->ioaddr +
1049 mmc_hostname(host->mmc), __func__);
1059 * turned on for host controllers using this DLL.
1062 config = readl_relaxed(host->ioaddr +
1065 writel_relaxed(config, host->ioaddr +
1075 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1080 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
1082 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1084 struct mmc_host *mmc = host->mmc;
1090 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
1096 ret = msm_init_cm_dll(host);
1102 ret = msm_config_cm_dll_phase(host,
1106 config = readl_relaxed(host->ioaddr +
1109 writel_relaxed(config, host->ioaddr +
1114 ret = sdhci_msm_cdclp533_calibration(host);
1116 ret = sdhci_msm_cm_dll_sdc4_calibration(host);
1118 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1123 static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host)
1125 struct mmc_ios *ios = &host->mmc->ios;
1131 if (host->clock <= CORE_FREQ_100MHZ ||
1141 static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host *host)
1143 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1151 if (!sdhci_msm_is_tuning_needed(host))
1155 ret = msm_init_cm_dll(host);
1160 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
1165 static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable)
1167 const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host);
1168 u32 config, oldconfig = readl_relaxed(host->ioaddr +
1181 writel_relaxed(config, host->ioaddr +
1188 struct sdhci_host *host = mmc_priv(mmc);
1192 struct mmc_ios ios = host->mmc->ios;
1193 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1196 if (!sdhci_msm_is_tuning_needed(host)) {
1198 sdhci_msm_set_cdr(host, false);
1216 if (host->flags & SDHCI_HS400_TUNING) {
1217 sdhci_msm_hc_select_mode(host);
1218 msm_set_clock_rate_for_bus_mode(host, ios.clock);
1219 host->flags &= ~SDHCI_HS400_TUNING;
1224 rc = msm_init_cm_dll(host);
1231 rc = msm_config_cm_dll_phase(host, phase);
1261 rc = msm_find_most_appropriate_phase(host, tuned_phases,
1272 rc = msm_config_cm_dll_phase(host, phase);
1298 static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
1300 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1304 if (host->clock > CORE_FREQ_100MHZ &&
1307 ret = sdhci_msm_hs400_dll_calibration(host);
1312 mmc_hostname(host->mmc), ret);
1316 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
1319 struct mmc_host *mmc = host->mmc;
1320 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1327 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1328 /* Select Bus Speed Mode for host */
1357 if (host->clock <= CORE_FREQ_100MHZ) {
1366 config = readl_relaxed(host->ioaddr +
1369 writel_relaxed(config, host->ioaddr +
1372 config = readl_relaxed(host->ioaddr +
1375 writel_relaxed(config, host->ioaddr +
1386 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
1387 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1390 sdhci_msm_hs400(host, &mmc->ios);
1515 static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
1517 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1525 mmc_hostname(host->mmc), __func__, req_type,
1535 val = msm_host_readl(msm_host, host,
1551 * for host->pwr to handle a case where IO voltage high request is
1554 if ((req_type & REQ_IO_HIGH) && !host->pwr) {
1556 mmc_hostname(host->mmc), req_type);
1574 mmc_hostname(host->mmc), req_type);
1576 pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc),
1580 static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)
1582 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1588 mmc_hostname(host->mmc),
1589 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),
1590 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),
1591 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));
1594 static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
1596 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1598 struct mmc_host *mmc = host->mmc;
1605 irq_status = msm_host_readl(msm_host, host,
1609 msm_host_writel(msm_host, irq_status, host,
1619 while (irq_status & msm_host_readl(msm_host, host,
1623 mmc_hostname(host->mmc), irq_status);
1624 sdhci_msm_dump_pwr_ctrl_regs(host);
1628 msm_host_writel(msm_host, irq_status, host,
1684 msm_host_writel(msm_host, irq_ack, host,
1704 config = readl_relaxed(host->ioaddr +
1716 writel_relaxed(new_config, host->ioaddr +
1732 struct sdhci_host *host = (struct sdhci_host *)data;
1733 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1736 sdhci_msm_handle_pwr_irq(host, irq);
1744 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
1746 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1753 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
1766 static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1770 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1780 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1781 sdhci_enable_clk(host, clk);
1784 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1785 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1787 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1791 host->mmc->actual_clock = msm_host->clk_rate = 0;
1795 sdhci_msm_hc_select_mode(host);
1797 msm_set_clock_rate_for_bus_mode(host, clock);
1799 __sdhci_msm_set_clock(host, clock);
1865 struct sdhci_host *host = mmc_priv(cq_host->mmc);
1866 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1917 static u32 sdhci_msm_cqe_irq(struct sdhci_host *host, u32 intmask)
1922 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1925 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1931 struct sdhci_host *host = mmc_priv(mmc);
1932 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1941 struct sdhci_host *host = mmc_priv(mmc);
1949 if (host->flags & SDHCI_USE_64_BIT_DMA)
1950 host->desc_sz = 16;
1952 spin_lock_irqsave(&host->lock, flags);
1960 ctrl = sdhci_readl(host, SDHCI_INT_ENABLE);
1962 sdhci_writel(host, ctrl, SDHCI_INT_ENABLE);
1963 sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
1965 spin_unlock_irqrestore(&host->lock, flags);
1970 static void sdhci_msm_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1974 __sdhci_set_timeout(host, cmd);
1975 count = sdhci_readb(host, SDHCI_TIMEOUT_CONTROL);
1979 * using 4 * MCLK * 2^(count + 13). where MCLK = 1 / host->clock.
1981 if (cmd && cmd->data && host->clock > 400000 &&
1982 host->clock <= 50000000 &&
1983 ((1 << (count + start)) > (10 * host->clock)))
1984 host->data_timeout = 22LL * NSEC_PER_SEC;
1995 static int sdhci_msm_cqe_add_host(struct sdhci_host *host,
1998 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2009 if (host->caps & SDHCI_CAN_64BIT)
2010 host->alloc_desc_sz = 16;
2012 ret = sdhci_setup_host(host);
2026 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
2032 ret = cqhci_init(cq_host, host->mmc, dma64);
2035 mmc_hostname(host->mmc), ret);
2050 if (host->flags & SDHCI_USE_64_BIT_DMA)
2051 host->desc_sz = 12;
2053 ret = __sdhci_add_host(host);
2058 mmc_hostname(host->mmc));
2062 sdhci_cleanup_host(host);
2073 static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)
2075 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2085 if (host->pwr && (val & SDHCI_RESET_ALL))
2099 sdhci_msm_set_cdr(host, true);
2101 sdhci_msm_set_cdr(host, false);
2117 static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)
2121 req_type = __sdhci_msm_check_write(host, val, reg);
2122 writew_relaxed(val, host->ioaddr + reg);
2125 sdhci_msm_check_power_status(host, req_type);
2129 static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)
2133 req_type = __sdhci_msm_check_write(host, val, reg);
2135 writeb_relaxed(val, host->ioaddr + reg);
2138 sdhci_msm_check_power_status(host, req_type);
2146 struct sdhci_host *host = mmc_priv(mmc);
2167 config = readl_relaxed(host->ioaddr +
2177 host->ioaddr + msm_offset->core_vendor_spec);
2199 struct sdhci_host *host = mmc_priv(mmc);
2206 if (host->version < SDHCI_SPEC_300)
2209 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2213 if (!(host->flags & SDHCI_SIGNALING_330))
2220 if (!(host->flags & SDHCI_SIGNALING_180))
2231 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2238 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2250 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
2252 static void sdhci_msm_dump_vendor_regs(struct sdhci_host *host)
2254 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2262 readl_relaxed(host->ioaddr + msm_offset->core_dll_status),
2263 readl_relaxed(host->ioaddr + msm_offset->core_dll_config),
2264 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2));
2267 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_3),
2268 readl_relaxed(host->ioaddr + msm_offset->core_dll_usr_ctl),
2269 readl_relaxed(host->ioaddr + msm_offset->core_ddr_config));
2272 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec),
2273 readl_relaxed(host->ioaddr +
2275 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3));
2347 struct sdhci_host *host)
2350 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2360 host->quirks2 |= SDHCI_QUIRK2_BROKEN_64_BIT_DMA;
2363 static int sdhci_msm_gcc_reset(struct device *dev, struct sdhci_host *host)
2403 struct sdhci_host *host;
2415 host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
2416 if (IS_ERR(host))
2417 return PTR_ERR(host);
2419 host->sdma_boundary = 0;
2420 pltfm_host = sdhci_priv(host);
2422 msm_host->mmc = host->mmc;
2425 ret = mmc_of_parse(host->mmc);
2430 * Based on the compatible string, load the required msm host info from
2443 sdhci_msm_get_of_property(pdev, host);
2447 ret = sdhci_msm_gcc_reset(&pdev->dev, host);
2537 host->ioaddr + msm_offset->core_vendor_spec);
2541 msm_host_writel(msm_host, HC_MODE_EN, host,
2543 config = msm_host_readl(msm_host, host,
2546 msm_host_writel(msm_host, config, host,
2550 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
2555 core_version = msm_host_readl(msm_host, host,
2578 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
2580 writel_relaxed(config, host->ioaddr +
2601 sdhci_msm_handle_pwr_irq(host, 0);
2618 msm_host_writel(msm_host, INT_MASK, host,
2623 dev_name(&pdev->dev), host);
2632 host->max_timeout_count = 0xF;
2641 host->mmc_host_ops.start_signal_voltage_switch =
2643 host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
2645 ret = sdhci_msm_cqe_add_host(host, pdev);
2647 ret = sdhci_add_host(host);
2673 struct sdhci_host *host = platform_get_drvdata(pdev);
2674 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2676 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
2679 sdhci_remove_host(host, dead);
2694 struct sdhci_host *host = dev_get_drvdata(dev);
2695 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2699 spin_lock_irqsave(&host->lock, flags);
2700 host->runtime_suspended = true;
2701 spin_unlock_irqrestore(&host->lock, flags);
2713 struct sdhci_host *host = dev_get_drvdata(dev);
2714 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2728 ret = sdhci_msm_restore_sdr_dll_config(host);
2739 spin_lock_irqsave(&host->lock, flags);
2740 host->runtime_suspended = false;
2741 spin_unlock_irqrestore(&host->lock, flags);