Lines Matching refs:afu
22 static int afu_control(struct cxl_afu *afu, u64 command, u64 clear,
29 spin_lock(&afu->afu_cntl_lock);
32 trace_cxl_afu_ctrl(afu, command);
34 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
35 cxl_p2n_write(afu, CXL_AFU_Cntl_An, (AFU_Cntl & ~clear) | command);
37 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
40 dev_warn(&afu->dev, "WARNING: AFU control timed out!\n");
45 if (!cxl_ops->link_ok(afu->adapter, afu)) {
46 afu->enabled = enabled;
54 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
63 cxl_p2n_write(afu, CXL_AFU_Cntl_An, AFU_Cntl & ~CXL_AFU_Cntl_An_RA);
67 afu->enabled = enabled;
69 trace_cxl_afu_ctrl_done(afu, command, rc);
70 spin_unlock(&afu->afu_cntl_lock);
75 static int afu_enable(struct cxl_afu *afu)
79 return afu_control(afu, CXL_AFU_Cntl_An_E, 0,
84 int cxl_afu_disable(struct cxl_afu *afu)
88 return afu_control(afu, 0, CXL_AFU_Cntl_An_E,
94 static int native_afu_reset(struct cxl_afu *afu)
101 rc = afu_control(afu, CXL_AFU_Cntl_An_RA, 0,
111 if (afu->current_mode == 0) {
112 serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
114 cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
120 static int native_afu_check_and_enable(struct cxl_afu *afu)
122 if (!cxl_ops->link_ok(afu->adapter, afu)) {
123 WARN(1, "Refusing to enable afu while link down!\n");
126 if (afu->enabled)
128 return afu_enable(afu);
131 int cxl_psl_purge(struct cxl_afu *afu)
133 u64 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
134 u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
141 trace_cxl_psl_ctrl(afu, CXL_PSL_SCNTL_An_Pc);
150 if (!cxl_ops->link_ok(afu->adapter, afu)) {
151 dev_warn(&afu->dev, "PSL Purge called with link down, ignoring\n");
158 cxl_afu_disable(afu);
161 cxl_p1n_write(afu, CXL_PSL_SCNTL_An,
164 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
168 dev_warn(&afu->dev, "WARNING: PSL Purge timed out!\n");
172 if (!cxl_ops->link_ok(afu->adapter, afu)) {
177 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
182 dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
183 dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n",
185 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
187 dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\n",
189 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
193 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
198 cxl_p1n_write(afu, CXL_PSL_SCNTL_An,
201 trace_cxl_psl_ctrl_done(afu, CXL_PSL_SCNTL_An_Pc, rc);
223 static int cxl_alloc_spa(struct cxl_afu *afu, int mode)
228 afu->native->spa_order = -1;
230 afu->native->spa_order++;
231 spa_size = (1 << afu->native->spa_order) * PAGE_SIZE;
234 dev_warn(&afu->dev, "num_of_processes too large for the SPA, limiting to %i (0x%x)\n",
235 afu->native->spa_max_procs, afu->native->spa_size);
237 afu->num_procs = afu->native->spa_max_procs;
241 afu->native->spa_size = spa_size;
242 afu->native->spa_max_procs = spa_max_procs(afu->native->spa_size);
243 } while (afu->native->spa_max_procs < afu->num_procs);
245 if (!(afu->native->spa = (struct cxl_process_element *)
246 __get_free_pages(GFP_KERNEL | __GFP_ZERO, afu->native->spa_order))) {
250 pr_devel("spa pages: %i afu->spa_max_procs: %i afu->num_procs: %i\n",
251 1<<afu->native->spa_order, afu->native->spa_max_procs, afu->num_procs);
256 static void attach_spa(struct cxl_afu *afu)
260 afu->native->sw_command_status = (__be64 *)((char *)afu->native->spa +
261 ((afu->native->spa_max_procs + 3) * 128));
263 spap = virt_to_phys(afu->native->spa) & CXL_PSL_SPAP_Addr;
264 spap |= ((afu->native->spa_size >> (12 - CXL_PSL_SPAP_Size_Shift)) - 1) & CXL_PSL_SPAP_Size;
267 afu->native->spa, afu->native->spa_max_procs,
268 afu->native->sw_command_status, spap);
269 cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap);
272 void cxl_release_spa(struct cxl_afu *afu)
274 if (afu->native->spa) {
275 free_pages((unsigned long) afu->native->spa,
276 afu->native->spa_order);
277 afu->native->spa = NULL;
383 static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1)
388 cxl_p2n_write(afu, CXL_SSTP1_An, 0);
391 if ((rc = cxl_afu_slbia(afu)))
395 cxl_p2n_write(afu, CXL_SSTP0_An, sstp0);
398 cxl_p2n_write(afu, CXL_SSTP1_An, sstp1);
406 struct cxl *adapter = ctx->afu->adapter;
409 WARN_ON(!mutex_is_locked(&ctx->afu->native->spa_mutex));
435 WARN_ON(!ctx->afu->enabled);
439 *(ctx->afu->native->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe);
441 cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe);
444 dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n");
448 if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) {
449 dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n");
453 state = be64_to_cpup(ctx->afu->native->sw_command_status);
481 mutex_lock(&ctx->afu->native->spa_mutex);
486 mutex_unlock(&ctx->afu->native->spa_mutex);
498 mutex_lock(&ctx->afu->native->spa_mutex);
504 if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu))
509 mutex_unlock(&ctx->afu->native->spa_mutex);
517 mutex_lock(&ctx->afu->native->spa_mutex);
523 if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu))
531 mutex_unlock(&ctx->afu->native->spa_mutex);
538 if (!ctx->afu->pp_size || ctx->master) {
539 ctx->psn_phys = ctx->afu->psn_phys;
540 ctx->psn_size = ctx->afu->adapter->ps_size;
542 ctx->psn_phys = ctx->afu->psn_phys +
543 (ctx->afu->native->pp_offset + ctx->afu->pp_size * ctx->pe);
544 ctx->psn_size = ctx->afu->pp_size;
548 static int activate_afu_directed(struct cxl_afu *afu)
552 dev_info(&afu->dev, "Activating AFU directed mode\n");
554 afu->num_procs = afu->max_procs_virtualised;
555 if (afu->native->spa == NULL) {
556 if (cxl_alloc_spa(afu, CXL_MODE_DIRECTED))
559 attach_spa(afu);
561 cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU);
563 cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);
564 cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L);
566 afu->current_mode = CXL_MODE_DIRECTED;
568 if ((rc = cxl_chardev_m_afu_add(afu)))
571 if ((rc = cxl_sysfs_afu_m_add(afu)))
574 if ((rc = cxl_chardev_s_afu_add(afu)))
579 cxl_sysfs_afu_m_remove(afu);
581 cxl_chardev_afu_remove(afu);
703 ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq;
725 result = cxl_ops->afu_check_and_enable(ctx->afu);
766 ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq;
776 if ((result = cxl_ops->afu_check_and_enable(ctx->afu)))
782 static int deactivate_afu_directed(struct cxl_afu *afu)
784 dev_info(&afu->dev, "Deactivating AFU directed mode\n");
786 afu->current_mode = 0;
787 afu->num_procs = 0;
789 cxl_sysfs_afu_m_remove(afu);
790 cxl_chardev_afu_remove(afu);
817 if (afu->adapter->native->sl_ops->needs_reset_before_disable)
818 cxl_ops->afu_reset(afu);
819 cxl_afu_disable(afu);
820 cxl_psl_purge(afu);
825 int cxl_activate_dedicated_process_psl9(struct cxl_afu *afu)
827 dev_info(&afu->dev, "Activating dedicated process mode\n");
836 afu->num_procs = 1;
837 if (afu->native->spa == NULL) {
838 if (cxl_alloc_spa(afu, CXL_MODE_DEDICATED))
841 attach_spa(afu);
843 cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process);
844 cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L);
846 afu->current_mode = CXL_MODE_DEDICATED;
848 return cxl_chardev_d_afu_add(afu);
851 int cxl_activate_dedicated_process_psl8(struct cxl_afu *afu)
853 dev_info(&afu->dev, "Activating dedicated process mode\n");
855 cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process);
857 cxl_p1n_write(afu, CXL_PSL_CtxTime_An, 0); /* disable */
858 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); /* disable */
859 cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);
860 cxl_p1n_write(afu, CXL_PSL_LPID_An, mfspr(SPRN_LPID));
861 cxl_p1n_write(afu, CXL_HAURP_An, 0); /* disable */
862 cxl_p1n_write(afu, CXL_PSL_SDR_An, mfspr(SPRN_SDR1));
864 cxl_p2n_write(afu, CXL_CSRP_An, 0); /* disable */
865 cxl_p2n_write(afu, CXL_AURP0_An, 0); /* disable */
866 cxl_p2n_write(afu, CXL_AURP1_An, 0); /* disable */
868 afu->current_mode = CXL_MODE_DEDICATED;
869 afu->num_procs = 1;
871 return cxl_chardev_d_afu_add(afu);
886 struct cxl_afu *afu = ctx->afu;
888 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An,
893 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, (u64)
902 struct cxl_afu *afu = ctx->afu;
910 if (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes)
911 afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx);
921 result = cxl_ops->afu_reset(afu);
925 return afu_enable(afu);
930 struct cxl_afu *afu = ctx->afu;
937 cxl_p2n_write(afu, CXL_PSL_PID_TID_An, pid);
939 cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx));
941 if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1)))
946 if (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes)
947 afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx);
949 cxl_p2n_write(afu, CXL_PSL_AMR_An, amr);
954 if ((rc = cxl_ops->afu_reset(afu)))
957 cxl_p2n_write(afu, CXL_PSL_WED_An, wed);
959 return afu_enable(afu);
962 static int deactivate_dedicated_process(struct cxl_afu *afu)
964 dev_info(&afu->dev, "Deactivating dedicated process mode\n");
966 afu->current_mode = 0;
967 afu->num_procs = 0;
969 cxl_chardev_afu_remove(afu);
974 static int native_afu_deactivate_mode(struct cxl_afu *afu, int mode)
977 return deactivate_afu_directed(afu);
979 return deactivate_dedicated_process(afu);
983 static int native_afu_activate_mode(struct cxl_afu *afu, int mode)
987 if (!(mode & afu->modes_supported))
990 if (!cxl_ops->link_ok(afu->adapter, afu)) {
996 return activate_afu_directed(afu);
998 (afu->adapter->native->sl_ops->activate_dedicated_process))
999 return afu->adapter->native->sl_ops->activate_dedicated_process(afu);
1007 if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) {
1013 if ((ctx->afu->current_mode == CXL_MODE_DIRECTED) &&
1014 (ctx->afu->adapter->native->sl_ops->attach_afu_directed))
1015 return ctx->afu->adapter->native->sl_ops->attach_afu_directed(ctx, wed, amr);
1017 if ((ctx->afu->current_mode == CXL_MODE_DEDICATED) &&
1018 (ctx->afu->adapter->native->sl_ops->attach_dedicated_process))
1019 return ctx->afu->adapter->native->sl_ops->attach_dedicated_process(ctx, wed, amr);
1029 * optional like we do in the afu directed path). It does not indicate
1042 cxl_ops->afu_reset(ctx->afu);
1043 cxl_afu_disable(ctx->afu);
1044 cxl_psl_purge(ctx->afu);
1050 if (ctx->afu->current_mode == CXL_MODE_DIRECTED)
1052 if ((ctx->afu->current_mode == CXL_MODE_DEDICATED) &&
1053 (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes))
1054 return ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx);
1074 if (ctx->afu->current_mode == CXL_MODE_DEDICATED)
1080 static int native_get_irq_info(struct cxl_afu *afu, struct cxl_irq_info *info)
1085 if (!cxl_ops->link_ok(afu->adapter, afu))
1088 info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1089 info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
1091 info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An);
1092 info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An);
1093 info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1103 fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL9_FIR1);
1105 dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1);
1106 if (ctx->afu->adapter->native->sl_ops->register_serr_irq) {
1107 serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);
1108 cxl_afu_decode_psl_serr(ctx->afu, serr);
1116 fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR1);
1117 fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR2);
1118 fir_slice = cxl_p1n_read(ctx->afu, CXL_PSL_FIR_SLICE_An);
1119 afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An);
1121 dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1);
1122 dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2);
1123 if (ctx->afu->adapter->native->sl_ops->register_serr_irq) {
1124 serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);
1125 cxl_afu_decode_psl_serr(ctx->afu, serr);
1127 dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice);
1128 dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug);
1135 dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%016llx\n", errstat);
1137 if (ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers)
1138 ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers(ctx);
1140 if (ctx->afu->adapter->native->sl_ops->debugfs_stop_trace) {
1141 dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n");
1142 ctx->afu->adapter->native->sl_ops->debugfs_stop_trace(ctx->afu->adapter);
1148 static bool cxl_is_translation_fault(struct cxl_afu *afu, u64 dsisr)
1159 irqreturn_t cxl_fail_irq_psl(struct cxl_afu *afu, struct cxl_irq_info *irq_info)
1161 if (cxl_is_translation_fault(afu, irq_info->dsisr))
1162 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1164 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1171 struct cxl_afu *afu = data;
1174 u64 phreg = cxl_p2n_read(afu, CXL_PSL_PEHandle_An);
1179 dev_warn(&afu->dev,
1186 if ((res = native_get_irq_info(afu, &irq_info))) {
1188 if (afu->adapter->native->sl_ops->fail_irq)
1189 return afu->adapter->native->sl_ops->fail_irq(afu, &irq_info);
1194 ctx = idr_find(&afu->contexts_idr, ph);
1196 if (afu->adapter->native->sl_ops->handle_interrupt)
1197 ret = afu->adapter->native->sl_ops->handle_interrupt(irq, ctx, &irq_info);
1207 if (afu->adapter->native->sl_ops->fail_irq)
1208 ret = afu->adapter->native->sl_ops->fail_irq(afu, &irq_info);
1223 ph = cxl_p2n_read(ctx->afu, CXL_PSL_PEHandle_An) & 0xffff;
1226 dsisr = cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An);
1240 dev_warn(&ctx->afu->dev, "WARNING: waiting on DSI for PE %i"
1247 struct cxl_afu *afu = data;
1254 serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1255 errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1256 afu_error = cxl_p2n_read(afu, CXL_AFU_ERR_An);
1257 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1258 cxl_afu_decode_psl_serr(afu, serr);
1261 fir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An);
1262 afu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An);
1263 dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice);
1264 dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug);
1266 dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%016llx\n", errstat);
1267 dev_crit(&afu->dev, "AFU_ERR_An: 0x%.16llx\n", afu_error);
1268 dev_crit(&afu->dev, "PSL_DSISR_An: 0x%.16llx\n", dsisr);
1273 cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
1274 dev_info(&afu->dev, "Further such interrupts will be masked until the AFU is reset\n");
1356 int cxl_native_register_serr_irq(struct cxl_afu *afu)
1361 afu->err_irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err",
1362 dev_name(&afu->dev));
1363 if (!afu->err_irq_name)
1366 if ((rc = cxl_register_one_irq(afu->adapter, native_slice_irq_err, afu,
1367 &afu->serr_hwirq,
1368 &afu->serr_virq, afu->err_irq_name))) {
1369 kfree(afu->err_irq_name);
1370 afu->err_irq_name = NULL;
1374 serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1376 serr = (serr & 0x00ffffffffff0000ULL) | (afu->serr_hwirq & 0xffff);
1382 serr = (serr & ~0xff0000007fffffffULL) | (afu->serr_hwirq & 0xffff);
1384 cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
1389 void cxl_native_release_serr_irq(struct cxl_afu *afu)
1391 if (afu->serr_virq == 0 ||
1392 afu->serr_virq != irq_find_mapping(NULL, afu->serr_hwirq))
1395 cxl_p1n_write(afu, CXL_PSL_SERR_An, 0x0000000000000000);
1396 cxl_unmap_irq(afu->serr_virq, afu);
1397 cxl_ops->release_one_irq(afu->adapter, afu->serr_hwirq);
1398 kfree(afu->err_irq_name);
1399 afu->serr_virq = 0;
1402 int cxl_native_register_psl_irq(struct cxl_afu *afu)
1406 afu->psl_irq_name = kasprintf(GFP_KERNEL, "cxl-%s",
1407 dev_name(&afu->dev));
1408 if (!afu->psl_irq_name)
1411 if ((rc = cxl_register_one_irq(afu->adapter, native_irq_multiplexed,
1412 afu, &afu->native->psl_hwirq, &afu->native->psl_virq,
1413 afu->psl_irq_name))) {
1414 kfree(afu->psl_irq_name);
1415 afu->psl_irq_name = NULL;
1420 void cxl_native_release_psl_irq(struct cxl_afu *afu)
1422 if (afu->native->psl_virq == 0 ||
1423 afu->native->psl_virq !=
1424 irq_find_mapping(NULL, afu->native->psl_hwirq))
1427 cxl_unmap_irq(afu->native->psl_virq, afu);
1428 cxl_ops->release_one_irq(afu->adapter, afu->native->psl_hwirq);
1429 kfree(afu->psl_irq_name);
1430 afu->native->psl_virq = 0;
1433 static void recover_psl_err(struct cxl_afu *afu, u64 errstat)
1440 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1441 cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE);
1444 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, errstat);
1451 cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc);
1453 recover_psl_err(ctx->afu, psl_reset_mask);
1458 int cxl_check_error(struct cxl_afu *afu)
1460 return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL);
1469 static int native_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off, u64 *out)
1471 if (unlikely(!cxl_ops->link_ok(afu->adapter, afu)))
1473 if (unlikely(off >= afu->crs_len))
1475 *out = in_le64(afu->native->afu_desc_mmio + afu->crs_offset +
1476 (cr * afu->crs_len) + off);
1480 static int native_afu_cr_read32(struct cxl_afu *afu, int cr, u64 off, u32 *out)
1482 if (unlikely(!cxl_ops->link_ok(afu->adapter, afu)))
1484 if (unlikely(off >= afu->crs_len))
1486 *out = in_le32(afu->native->afu_desc_mmio + afu->crs_offset +
1487 (cr * afu->crs_len) + off);
1491 static int native_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off, u16 *out)
1497 rc = native_afu_cr_read32(afu, cr, aligned_off, &val);
1503 static int native_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off, u8 *out)
1509 rc = native_afu_cr_read32(afu, cr, aligned_off, &val);
1515 static int native_afu_cr_write32(struct cxl_afu *afu, int cr, u64 off, u32 in)
1517 if (unlikely(!cxl_ops->link_ok(afu->adapter, afu)))
1519 if (unlikely(off >= afu->crs_len))
1521 out_le32(afu->native->afu_desc_mmio + afu->crs_offset +
1522 (cr * afu->crs_len) + off, in);
1526 static int native_afu_cr_write16(struct cxl_afu *afu, int cr, u64 off, u16 in)
1532 rc = native_afu_cr_read32(afu, cr, aligned_off, &val32);
1540 rc = native_afu_cr_write32(afu, cr, aligned_off, val32);
1544 static int native_afu_cr_write8(struct cxl_afu *afu, int cr, u64 off, u8 in)
1550 rc = native_afu_cr_read32(afu, cr, aligned_off, &val32);
1557 rc = native_afu_cr_write32(afu, cr, aligned_off, val32);