Lines Matching refs:pll
3 * drivers/media/i2c/ccs-pll.c
17 #include "ccs-pll.h"
78 static void print_pll(struct device *dev, struct ccs_pll *pll)
85 { &pll->vt_fr, &pll->vt_bk, PLL_VT },
86 { &pll->op_fr, &pll->op_bk, PLL_OP }
90 dev_dbg(dev, "ext_clk_freq_hz\t\t%u\n", pll->ext_clk_freq_hz);
95 if (pll->flags & CCS_PLL_FLAG_DUAL_PLL ||
108 if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) ||
123 pll->pixel_rate_pixel_array);
125 pll->pixel_rate_csi);
128 pll->flags & PLL_FL(LANE_SPEED_MODEL) ? " lane-speed" : "",
129 pll->flags & PLL_FL(LINK_DECOUPLED) ? " link-decoupled" : "",
130 pll->flags & PLL_FL(EXT_IP_PLL_DIVIDER) ?
131 " ext-ip-pll-divider" : "",
132 pll->flags & PLL_FL(FLEXIBLE_OP_PIX_CLK_DIV) ?
134 pll->flags & PLL_FL(FIFO_DERATING) ? " fifo-derating" : "",
135 pll->flags & PLL_FL(FIFO_OVERRATING) ? " fifo-overrating" : "",
136 pll->flags & PLL_FL(DUAL_PLL) ? " dual-pll" : "",
137 pll->flags & PLL_FL(OP_SYS_DDR) ? " op-sys-ddr" : "",
138 pll->flags & PLL_FL(OP_PIX_DDR) ? " op-pix-ddr" : "");
153 struct ccs_pll *pll, unsigned int which)
162 pll_fr = &pll->op_fr;
165 pll_fr = &pll->vt_fr;
193 struct ccs_pll *pll, unsigned int which)
201 if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
205 pll_bk = &pll->op_bk;
208 pll_bk = &pll->vt_bk;
233 static int check_ext_bounds(struct device *dev, struct ccs_pll *pll)
235 if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING) &&
236 pll->pixel_rate_pixel_array > pll->pixel_rate_csi) {
241 if (!(pll->flags & CCS_PLL_FLAG_FIFO_OVERRATING) &&
242 pll->pixel_rate_pixel_array < pll->pixel_rate_csi) {
252 struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
292 struct ccs_pll *pll, u32 mul, u32 div)
296 struct ccs_pll_branch_fr *pll_fr = &pll->vt_fr;
297 struct ccs_pll_branch_bk *pll_bk = &pll->vt_bk;
303 pll->ext_clk_freq_hz / pll_fr->pre_pll_clk_div;
325 ccs_pll_find_vt_sys_div(dev, lim, pll, pll_fr, vt_div, vt_div,
370 pll->pixel_rate_pixel_array =
371 pll_bk->pix_clk_freq_hz * pll->vt_lanes;
378 struct ccs_pll *pll)
381 struct ccs_pll_branch_fr *pll_fr = &pll->vt_fr;
386 pre_div = gcd(pll->pixel_rate_csi,
387 pll->ext_clk_freq_hz * pll->vt_lanes);
388 pre_mul = pll->pixel_rate_csi / pre_div;
389 pre_div = pll->ext_clk_freq_hz * pll->vt_lanes / pre_div;
394 DIV_ROUND_UP(pll->ext_clk_freq_hz,
398 pll->ext_clk_freq_hz /
407 (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
419 rval = __ccs_pll_calculate_vt_tree(dev, lim, pll,
424 rval = check_fr_bounds(dev, lim, pll, PLL_VT);
428 rval = check_bk_bounds(dev, lim, pll, PLL_VT);
441 struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
451 if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
458 if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING)) {
461 * pll->vt_lanes * phy_const / pll->op_lanes
462 / (PHY_CONST_DIV << op_pix_ddr(pll->flags));
472 / pll->binning_horizontal)
473 vt_op_binning_div = pll->binning_horizontal;
489 dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
491 DIV_ROUND_UP(pll->bits_per_pixel
492 * op_pll_bk->sys_clk_div * pll->scale_n
493 * pll->vt_lanes * phy_const,
494 (pll->flags &
496 pll->csi2.lanes : 1)
497 * vt_op_binning_div * pll->scale_m
498 * PHY_CONST_DIV << op_pix_ddr(pll->flags));
520 ccs_pll_find_vt_sys_div(dev, lim, pll, pll_fr, min_vt_div,
562 pll->vt_bk.sys_clk_div = DIV_ROUND_UP(vt_div, best_pix_div);
563 pll->vt_bk.pix_clk_div = best_pix_div;
565 pll->vt_bk.sys_clk_freq_hz =
566 pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div;
567 pll->vt_bk.pix_clk_freq_hz =
568 pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div;
571 pll->pixel_rate_pixel_array =
572 pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes;
590 struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr,
611 /* Don't go above max pll multiplier. */
615 /* Don't go above max pll op frequency. */
620 / (pll->ext_clk_freq_hz /
637 pll->ext_clk_freq_hz /
672 op_pll_fr->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz
678 if (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)
680 (pll->bits_per_pixel
681 * pll->op_lanes * (phy_const << op_sys_ddr(pll->flags))
682 / PHY_CONST_DIV / pll->csi2.lanes / l)
683 >> op_pix_ddr(pll->flags);
686 (pll->bits_per_pixel
687 * (phy_const << op_sys_ddr(pll->flags))
688 / PHY_CONST_DIV / l) >> op_pix_ddr(pll->flags);
691 (op_sys_clk_freq_hz_sdr >> op_pix_ddr(pll->flags))
694 op_sys_clk_freq_hz_sdr >> op_sys_ddr(pll->flags);
702 struct ccs_pll *pll)
708 bool cphy = pll->bus_type == CCS_PLL_BUS_TYPE_CSI2_CPHY;
714 u32 l = (!pll->op_bits_per_lane ||
715 pll->op_bits_per_lane >= pll->bits_per_pixel) ? 1 : 2;
719 if (!(pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)) {
720 pll->op_lanes = 1;
721 pll->vt_lanes = 1;
724 if (pll->flags & CCS_PLL_FLAG_DUAL_PLL) {
727 op_pll_fr = &pll->op_fr;
728 op_pll_bk = &pll->op_bk;
729 } else if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
737 op_pll_fr = &pll->vt_fr;
738 op_pll_bk = &pll->vt_bk;
742 op_pll_fr = &pll->vt_fr;
743 op_pll_bk = &pll->op_bk;
746 if (!pll->op_lanes || !pll->vt_lanes || !pll->bits_per_pixel ||
747 !pll->ext_clk_freq_hz || !pll->link_freq || !pll->scale_m ||
759 if (!(pll->flags & CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV) &&
760 (pll->bits_per_pixel * pll->op_lanes) %
761 (pll->csi2.lanes * l << op_pix_ddr(pll->flags))) {
763 pll->bits_per_pixel, pll->op_lanes, pll->csi2.lanes, l);
767 dev_dbg(dev, "vt_lanes: %u\n", pll->vt_lanes);
768 dev_dbg(dev, "op_lanes: %u\n", pll->op_lanes);
770 dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal,
771 pll->binning_vertical);
773 switch (pll->bus_type) {
776 op_sys_clk_freq_hz_sdr = pll->link_freq * 2
777 * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
778 1 : pll->csi2.lanes);
784 pll->pixel_rate_csi =
786 * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
787 pll->csi2.lanes : 1) * PHY_CONST_DIV,
788 phy_const * pll->bits_per_pixel * l);
790 /* Figure out limits for OP pre-pll divider based on extclk */
795 clk_div_even(pll->ext_clk_freq_hz /
800 DIV_ROUND_UP(pll->ext_clk_freq_hz,
802 dev_dbg(dev, "pre-pll check: min / max op_pre_pll_clk_div: %u / %u\n",
806 pll->ext_clk_freq_hz << op_pix_ddr(pll->flags));
808 div = (pll->ext_clk_freq_hz << op_pix_ddr(pll->flags)) / i;
817 pll->ext_clk_freq_hz))));
824 (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
826 rval = ccs_pll_calculate_op(dev, lim, op_lim_fr, op_lim_bk, pll,
833 rval = check_fr_bounds(dev, lim, pll,
834 pll->flags & CCS_PLL_FLAG_DUAL_PLL ?
839 rval = check_bk_bounds(dev, lim, pll, PLL_OP);
843 if (pll->flags & CCS_PLL_FLAG_DUAL_PLL)
846 ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr,
849 rval = check_bk_bounds(dev, lim, pll, PLL_VT);
852 rval = check_ext_bounds(dev, pll);
865 if (pll->flags & CCS_PLL_FLAG_DUAL_PLL) {
866 rval = ccs_pll_calculate_vt_tree(dev, lim, pll);
872 print_pll(dev, pll);