drivers/irqchip/irq-apple-aic.c

796 static int __init aic_init_smp(struct aic_irq_chip *irqc, struct device_node *node)
918 	struct aic_irq_chip *irqc;
926 	irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
927 	if (!irqc) {
932 	irqc->base = regs;
938 	irqc->info = *(struct aic_info *)match->data;
940 	aic_irqc = irqc;
942 	switch (irqc->info.version) {
946 		info = aic_ic_read(irqc, AIC_INFO);
947 		irqc->nr_irq = FIELD_GET(AIC_INFO_NR_IRQ, info);
948 		irqc->max_irq = AIC_MAX_IRQ;
949 		irqc->nr_die = irqc->max_die = 1;
951 		off = start_off = irqc->info.target_cpu;
952 		off += sizeof(u32) * irqc->max_irq; /* TARGET_CPU */
954 		irqc->event = irqc->base;
961 		info1 = aic_ic_read(irqc, AIC2_INFO1);
962 		info3 = aic_ic_read(irqc, AIC2_INFO3);
964 		irqc->nr_irq = FIELD_GET(AIC2_INFO1_NR_IRQ, info1);
965 		irqc->max_irq = FIELD_GET(AIC2_INFO3_MAX_IRQ, info3);
966 		irqc->nr_die = FIELD_GET(AIC2_INFO1_LAST_DIE, info1) + 1;
967 		irqc->max_die = FIELD_GET(AIC2_INFO3_MAX_DIE, info3);
969 		off = start_off = irqc->info.irq_cfg;
970 		off += sizeof(u32) * irqc->max_irq; /* IRQ_CFG */
972 		irqc->event = of_iomap(node, 1);
973 		if (WARN_ON(!irqc->event))
980 	irqc->info.sw_set = off;
981 	off += sizeof(u32) * (irqc->max_irq >> 5); /* SW_SET */
982 	irqc->info.sw_clr = off;
983 	off += sizeof(u32) * (irqc->max_irq >> 5); /* SW_CLR */
984 	irqc->info.mask_set = off;
985 	off += sizeof(u32) * (irqc->max_irq >> 5); /* MASK_SET */
986 	irqc->info.mask_clr = off;
987 	off += sizeof(u32) * (irqc->max_irq >> 5); /* MASK_CLR */
988 	off += sizeof(u32) * (irqc->max_irq >> 5); /* HW_STATE */
990 	if (irqc->info.fast_ipi)
995 	irqc->info.die_stride = off - start_off;
997 	irqc->hw_domain = irq_domain_create_tree(of_node_to_fwnode(node),
998 						 &aic_irq_domain_ops, irqc);
999 	if (WARN_ON(!irqc->hw_domain))
1002 	irq_domain_update_bus_token(irqc->hw_domain, DOMAIN_BUS_WIRED);
1004 	if (aic_init_smp(irqc, node))
1012 			build_fiq_affinity(irqc, chld);
1020 	for (die = 0; die < irqc->nr_die; die++) {
1021 		for (i = 0; i < BITS_TO_U32(irqc->nr_irq); i++)
1022 			aic_ic_write(irqc, irqc->info.mask_set + off + i * 4, U32_MAX);
1023 		for (i = 0; i < BITS_TO_U32(irqc->nr_irq); i++)
1024 			aic_ic_write(irqc, irqc->info.sw_clr + off + i * 4, U32_MAX);
1025 		if (irqc->info.target_cpu)
1026 			for (i = 0; i < irqc->nr_irq; i++)
1027 				aic_ic_write(irqc, irqc->info.target_cpu + off + i * 4, 1);
1028 		off += irqc->info.die_stride;
1031 	if (irqc->info.version == 2) {
1032 		u32 config = aic_ic_read(irqc, AIC2_CONFIG);
1035 		aic_ic_write(irqc, AIC2_CONFIG, config);
1066 		irqc->nr_irq, irqc->max_irq, irqc->nr_die, irqc->max_die, AIC_NR_FIQ, AIC_NR_SWIPI);
1071 	irq_domain_remove(irqc->hw_domain);
1073 	if (irqc->event && irqc->event != irqc->base)
1074 		iounmap(irqc->event);
1075 	iounmap(irqc->base);
1076 	kfree(irqc);