input/misc/iqs626a.c

446 	struct iqs626_sys_reg sys_reg;
463 	struct iqs626_sys_reg *sys_reg = &iqs626->sys_reg;
473 		thresh = sys_reg->ch_reg_ulp.thresh;
474 		hyst = &sys_reg->ch_reg_ulp.hyst;
479 		thresh = &sys_reg->tp_grp_reg.ch_reg_tp[0].thresh;
480 		hyst = &sys_reg->tp_grp_reg.hyst;
487 		thresh = sys_reg->ch_reg_gen[i].thresh;
488 		hyst = &sys_reg->ch_reg_gen[i].hyst;
492 		thresh = &sys_reg->ch_reg_hall.thresh;
493 		hyst = &sys_reg->ch_reg_hall.hyst;
539 				sys_reg->event_mask &= ~iqs626_events[i].mask;
589 	struct iqs626_sys_reg *sys_reg = &iqs626->sys_reg;
597 		ati_target = &sys_reg->ch_reg_ulp.ati_target;
602 		ati_target = &sys_reg->tp_grp_reg.ati_target;
609 		ati_target = &sys_reg->ch_reg_gen[i].ati_target;
613 		ati_target = &sys_reg->ch_reg_hall.ati_target;
717 	struct iqs626_sys_reg *sys_reg = &iqs626->sys_reg;
719 	u8 *hyst = &sys_reg->tp_grp_reg.hyst;
731 		sys_reg->misc_a &= ~IQS626_MISC_A_TPx_LTA_UPDATE_MASK;
732 		sys_reg->misc_a |= (val << IQS626_MISC_A_TPx_LTA_UPDATE_SHIFT);
744 		sys_reg->misc_b &= ~IQS626_MISC_B_FILT_STR_TPx;
745 		sys_reg->misc_b |= val;
775 		u8 *ati_base = &sys_reg->tp_grp_reg.ch_reg_tp[i].ati_base;
776 		u8 *thresh = &sys_reg->tp_grp_reg.ch_reg_tp[i].thresh;
835 	sys_reg->misc_b &= ~IQS626_MISC_B_TPx_SWIPE;
837 		sys_reg->misc_b |= IQS626_MISC_B_TPx_SWIPE;
848 		sys_reg->timeout_tap = val / 16;
860 		sys_reg->timeout_swipe = val / 16;
872 		sys_reg->thresh_swipe = val;
875 	sys_reg->event_mask &= ~IQS626_EVENT_MASK_GESTURE;
884 	struct iqs626_sys_reg *sys_reg = &iqs626->sys_reg;
893 		engine = sys_reg->ch_reg_ulp.engine;
898 		engine = sys_reg->tp_grp_reg.engine;
905 		engine = sys_reg->ch_reg_gen[i].engine;
909 		engine = &sys_reg->ch_reg_hall.engine;
925 		sys_reg->redo_ati |= iqs626_channels[ch_id].active;
928 		sys_reg->reseed |= iqs626_channels[ch_id].active;
1066 		sys_reg->ch_reg_ulp.hyst &= ~IQS626_ULP_PROJ_ENABLE;
1068 			sys_reg->ch_reg_ulp.hyst |= IQS626_ULP_PROJ_ENABLE;
1070 		filter = &sys_reg->ch_reg_ulp.filter;
1072 		rx_enable = &sys_reg->ch_reg_ulp.rx_enable;
1073 		tx_enable = &sys_reg->ch_reg_ulp.tx_enable;
1076 		filter = &sys_reg->ch_reg_gen[i].filter;
1078 		rx_enable = &sys_reg->ch_reg_gen[i].rx_enable;
1079 		tx_enable = &sys_reg->ch_reg_gen[i].tx_enable;
1202 	assoc_select = &sys_reg->ch_reg_gen[i].assoc_select;
1203 	assoc_weight = &sys_reg->ch_reg_gen[i].assoc_weight;
1234 	struct iqs626_sys_reg *sys_reg = &iqs626->sys_reg;
1252 	error = regmap_raw_read(iqs626->regmap, IQS626_SYS_SETTINGS, sys_reg,
1253 				sizeof(*sys_reg));
1257 	general = be16_to_cpu(sys_reg->general);
1277 	sys_reg->misc_a &= ~IQS626_MISC_A_ATI_BAND_DISABLE;
1279 		sys_reg->misc_a |= IQS626_MISC_A_ATI_BAND_DISABLE;
1281 	sys_reg->misc_a &= ~IQS626_MISC_A_ATI_LP_ONLY;
1283 		sys_reg->misc_a |= IQS626_MISC_A_ATI_LP_ONLY;
1293 		sys_reg->misc_a &= ~IQS626_MISC_A_GPIO3_SELECT_MASK;
1294 		sys_reg->misc_a |= val;
1305 		sys_reg->misc_b &= ~IQS626_MISC_B_RESEED_UI_SEL_MASK;
1306 		sys_reg->misc_b |= (val << IQS626_MISC_B_RESEED_UI_SEL_SHIFT);
1309 	sys_reg->misc_b &= ~IQS626_MISC_B_THRESH_EXTEND;
1311 		sys_reg->misc_b |= IQS626_MISC_B_THRESH_EXTEND;
1313 	sys_reg->misc_b &= ~IQS626_MISC_B_TRACKING_UI_ENABLE;
1315 		sys_reg->misc_b |= IQS626_MISC_B_TRACKING_UI_ENABLE;
1317 	sys_reg->misc_b &= ~IQS626_MISC_B_RESEED_OFFSET;
1319 		sys_reg->misc_b |= IQS626_MISC_B_RESEED_OFFSET;
1328 		sys_reg->rate_np = val;
1338 		sys_reg->rate_lp = val;
1348 		sys_reg->rate_ulp = val / 16;
1358 		sys_reg->timeout_pwr = val / 512;
1368 		sys_reg->timeout_lta = val / 512;
1371 	sys_reg->event_mask = ~((u8)IQS626_EVENT_MASK_SYS);
1372 	sys_reg->redo_ati = 0;
1374 	sys_reg->reseed = 0;
1375 	sys_reg->active = 0;
1388 		sys_reg->active |= iqs626_channels[i].active;
1398 	if (sys_reg->active & iqs626_channels[IQS626_CH_TP_2].active &&
1399 	    sys_reg->event_mask & IQS626_EVENT_MASK_GESTURE)
1405 	sys_reg->general = cpu_to_be16(general);
1408 				 &iqs626->sys_reg, sizeof(iqs626->sys_reg));
1419 	struct iqs626_sys_reg *sys_reg = &iqs626->sys_reg;
1435 		if (!(sys_reg->active & iqs626_channels[i].active))
1448 	if (!(sys_reg->active & iqs626_channels[IQS626_CH_TP_2].active))
1466 	if (sys_reg->event_mask & IQS626_EVENT_MASK_GESTURE) {
1472 		if ((sys_reg->active & tp_mask) == tp_mask)
1498 	struct iqs626_sys_reg *sys_reg = &iqs626->sys_reg;
1523 					 sys_reg, sizeof(*sys_reg));
1539 	if (sys_reg->active & iqs626_channels[IQS626_CH_HALL].active) {
1554 		if (!(sys_reg->active & iqs626_channels[i].active))
1579 	if (!(sys_reg->active & iqs626_channels[IQS626_CH_TP_2].active))
1582 	if (sys_reg->event_mask & IQS626_EVENT_MASK_GESTURE) {