Lines Matching defs:write_csr
1316 * write_csr - write CSR at the indicated offset
1321 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value)
1358 write_csr(dd, csr, value);
5684 write_csr(dd, SEND_EGRESS_ERR_INFO, info);
6100 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6136 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6191 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
6202 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
6326 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0,
6348 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0);
6369 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_INTO_RESET);
6375 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET);
6403 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
6424 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
6426 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf
6440 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
6441 write_csr(dd, SEND_CM_CREDIT_VL15, 0);
6442 write_csr(dd, SEND_CM_GLOBAL_CREDIT, 0);
6481 write_csr(dd, DC_LCB_CFG_RUN, 0);
6483 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET,
6488 write_csr(dd, DCC_CFG_RESET, reg |
6493 write_csr(dd, DCC_CFG_RESET, reg);
6494 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6523 write_csr(dd, DC_DC8051_CFG_RST, 0x1);
6547 write_csr(dd, DC_DC8051_CFG_RST, 0ull);
6554 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET);
6556 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6634 write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull);
6645 write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr);
6647 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
6649 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr);
6722 write_csr(dd, RCV_CTRL, rcvctrl);
6747 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6896 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6900 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6902 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
7500 write_csr(dd, DC_LCB_CFG_CRC_MODE,
7506 write_csr(dd, SEND_CM_CTRL,
7509 write_csr(dd, SEND_CM_CTRL,
7570 write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg);
7574 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
7577 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
7845 write_csr(dd, DC_DC8051_ERR_EN,
8308 write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]);
8341 write_csr(dd,
8364 write_csr(dd, addr, rcd->imask);
8372 write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask);
8565 write_csr(dd, DCC_CFG_PORT_CONFIG, reg);
8673 write_csr(dd, addr, data);
8703 write_csr(dd, addr, data);
8776 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg);
8787 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8789 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8826 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0);
9200 write_csr(dd, DC_LCB_CFG_LOOPBACK,
9202 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
9207 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
9212 write_csr(dd, DC_LCB_CFG_RUN,
9219 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP,
9237 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
9252 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
9270 write_csr(dd, DC_DC8051_CFG_MODE,
9512 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
9518 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask);
9535 write_csr(dd,
9541 write_csr(dd,
9729 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
9731 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK,
9739 write_csr(dd,
9762 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01);
9763 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00);
9764 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00);
9765 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
9766 write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08);
9767 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02);
9768 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00);
10140 write_csr(dd, SEND_LEN_CHECK0, len1);
10141 write_csr(dd, SEND_LEN_CHECK1, len2);
10167 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1);
10190 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1);
10369 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1);
10370 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
10373 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
10374 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0);
10375 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
10376 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x2);
10378 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
10381 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 1);
10382 write_csr(dd, DC_LCB_CFG_RUN, 1ull << DC_LCB_CFG_RUN_EN_SHIFT);
10389 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1);
10390 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 0);
10391 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 0);
10466 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
10822 write_csr(dd, DCC_CFG_LED_CNTRL, 0);
10986 write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg);
11158 write_csr(dd, target + (i * 8), reg);
11254 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0,
11272 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16,
11308 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
11319 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
11336 write_csr(dd, addr, reg);
11353 write_csr(dd, addr, reg);
12076 write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT);
12079 write_csr(dd, RCV_VL15, 0);
13196 write_csr(dd, CCE_INT_MASK + (8 * idx), reg);
13243 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0);
13245 write_csr(dd, CCE_ERR_CLEAR, ~(u64)0);
13246 write_csr(dd, MISC_ERR_CLEAR, ~(u64)0);
13247 write_csr(dd, RCV_ERR_CLEAR, ~(u64)0);
13248 write_csr(dd, SEND_ERR_CLEAR, ~(u64)0);
13249 write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0);
13250 write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0);
13251 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0);
13257 write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0);
13258 write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0);
13259 write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0);
13287 write_csr(dd, CCE_INT_MAP + (8 * m), reg);
13318 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
13541 write_csr(dd, RCV_PARTITION_KEY +
13565 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
13594 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
13612 write_csr(dd, CCE_CTRL, ctrl_bits);
13643 write_csr(dd, CCE_SCRATCH + (8 * i), 0);
13645 write_csr(dd, CCE_ERR_MASK, 0);
13646 write_csr(dd, CCE_ERR_CLEAR, ~0ull);
13649 write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0);
13650 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR);
13653 write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0);
13654 write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i),
13659 write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull);
13660 write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull);
13663 write_csr(dd, CCE_INT_MAP, 0);
13666 write_csr(dd, CCE_INT_MASK + (8 * i), 0);
13667 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull);
13672 write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0);
13681 write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0);
13682 write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0);
13683 write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0);
13690 write_csr(dd, MISC_CFG_RSA_CMD, 1);
13691 write_csr(dd, MISC_CFG_RSA_MU, 0);
13692 write_csr(dd, MISC_CFG_FW_CTRL, 0);
13698 write_csr(dd, MISC_ERR_MASK, 0);
13699 write_csr(dd, MISC_ERR_CLEAR, ~0ull);
13711 write_csr(dd, SEND_CTRL, 0);
13717 write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0);
13720 write_csr(dd, SEND_PIO_ERR_MASK, 0);
13721 write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull);
13724 write_csr(dd, SEND_DMA_ERR_MASK, 0);
13725 write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull);
13728 write_csr(dd, SEND_EGRESS_ERR_MASK, 0);
13729 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull);
13731 write_csr(dd, SEND_BTH_QP, 0);
13732 write_csr(dd, SEND_STATIC_RATE_CONTROL, 0);
13733 write_csr(dd, SEND_SC2VLT0, 0);
13734 write_csr(dd, SEND_SC2VLT1, 0);
13735 write_csr(dd, SEND_SC2VLT2, 0);
13736 write_csr(dd, SEND_SC2VLT3, 0);
13737 write_csr(dd, SEND_LEN_CHECK0, 0);
13738 write_csr(dd, SEND_LEN_CHECK1, 0);
13740 write_csr(dd, SEND_ERR_MASK, 0);
13741 write_csr(dd, SEND_ERR_CLEAR, ~0ull);
13744 write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0);
13746 write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0);
13748 write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0);
13750 write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0);
13752 write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0);
13753 write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR);
13754 write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR);
13756 write_csr(dd, SEND_CM_TIMER_CTRL, 0);
13757 write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0);
13758 write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0);
13759 write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0);
13760 write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0);
13762 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
13763 write_csr(dd, SEND_CM_CREDIT_VL15, 0);
13768 write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull);
13856 write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK);
13893 write_csr(dd, RCV_CTRL, 0);
13899 write_csr(dd, RCV_BTH_QP, 0);
13900 write_csr(dd, RCV_MULTICAST, 0);
13901 write_csr(dd, RCV_BYPASS, 0);
13902 write_csr(dd, RCV_VL15, 0);
13904 write_csr(dd, RCV_ERR_INFO,
13907 write_csr(dd, RCV_ERR_MASK, 0);
13908 write_csr(dd, RCV_ERR_CLEAR, ~0ull);
13911 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
13913 write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0);
13915 write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0);
13917 write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0);
13921 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0);
13971 write_csr(dd, SEND_SC2VLT0, SC2VL_VAL(
13977 write_csr(dd, SEND_SC2VLT1, SC2VL_VAL(
13983 write_csr(dd, SEND_SC2VLT2, SC2VL_VAL(
13989 write_csr(dd, SEND_SC2VLT3, SC2VL_VAL(
13997 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL(
14001 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL(
14041 write_csr(dd, SEND_CTRL, 0);
14047 write_csr(dd, RCV_CTRL, 0);
14049 write_csr(dd, RCV_CTXT_CTRL, 0);
14052 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
14060 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
14100 write_csr(dd, CCE_DC_CTRL, 0);
14115 write_csr(dd, ASIC_QSFP1_OUT, 0x1f);
14116 write_csr(dd, ASIC_QSFP2_OUT, 0x1f);
14149 write_csr(dd, SEND_BTH_QP,
14153 write_csr(dd, RCV_BTH_QP,
14203 write_csr(dd, regno, reg);
14263 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]);
14282 write_csr(dd, RCV_RSM_CFG + (8 * rule_index),
14286 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index),
14293 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index),
14305 write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 0);
14306 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 0);
14307 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 0);
14558 write_csr(dd, regoff, reg);
14652 write_csr(dd, RCV_ERR_MASK, ~0ull);
14683 write_csr(dd, RCV_BYPASS, val);
14690 write_csr(dd, CCE_ERR_MASK, ~0ull);
14692 write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK);
14694 write_csr(dd, DCC_ERR_FLG_EN, ~0ull);
14695 write_csr(dd, DC_DC8051_ERR_EN, ~0ull);
14709 write_csr(dd, csr0to3,
14716 write_csr(dd, csr4to7,
14744 write_csr(dd, SEND_PIO_ERR_MASK, ~0ull);
14745 write_csr(dd, SEND_DMA_ERR_MASK, ~0ull);
14746 write_csr(dd, SEND_ERR_MASK, ~0ull);
14747 write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull);
14763 write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE);
14965 write_csr(dd, CCE_INT_MASK, 0ull);
14971 write_csr(dd, CCE_INT_CLEAR, all_bits);
14977 write_csr(dd, CCE_INT_FORCE, all_bits);
14983 write_csr(dd, CCE_INT_CLEAR, all_bits);
14984 write_csr(dd, CCE_INT_MASK, mask);
14988 write_csr(dd, CCE_INT_MASK, mask);
15415 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
15458 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);