iio/accel/sca3000.c

310 	int ret;
312 	ret = sca3000_read_data_short(st, SCA3000_REG_STATUS_ADDR, 1);
313 	if (ret < 0)
314 		return ret;
368 	int ret;
370 	ret = sca3000_reg_lock_on(st);
371 	if (ret < 0)
373 	if (ret) {
374 		ret = __sca3000_unlock_reg_lock(st);
375 		if (ret)
380 	ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, sel);
381 	if (ret)
385 	ret = sca3000_write_reg(st, SCA3000_REG_CTRL_DATA_ADDR, val);
388 	return ret;
401 	int ret;
403 	ret = sca3000_reg_lock_on(st);
404 	if (ret < 0)
406 	if (ret) {
407 		ret = __sca3000_unlock_reg_lock(st);
408 		if (ret)
412 	ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, ctrl_reg);
413 	if (ret)
415 	ret = sca3000_read_data_short(st, SCA3000_REG_CTRL_DATA_ADDR, 1);
416 	if (ret)
420 	return ret;
431 	int ret;
435 	ret = sca3000_read_data_short(st, SCA3000_REG_REVID_ADDR, 1);
436 	if (ret < 0)
445 	return ret;
576 	int ret;
578 	ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
579 	if (ret)
592 		ret = -EINVAL;
595 	return ret;
607 	int ret;
609 	ret = __sca3000_get_base_freq(st, st->info, val);
610 	if (ret)
611 		return ret;
613 	ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
614 	if (ret < 0)
615 		return ret;
618 		ret &= SCA3000_REG_OUT_CTRL_BUF_DIV_MASK;
619 		switch (ret) {
641 	int ret, base_freq, ctrlval;
643 	ret = __sca3000_get_base_freq(st, st->info, &base_freq);
644 	if (ret)
645 		return ret;
647 	ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
648 	if (ret < 0)
649 		return ret;
651 	ctrlval = ret & ~SCA3000_REG_OUT_CTRL_BUF_DIV_MASK;
666 	int ret;
668 	ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
669 	if (ret)
670 		return ret;
693 	int ret;
706 	ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
707 	if (ret)
708 		return ret;
723 	int ret;
735 			ret = sca3000_read_data_short(st, address, 2);
736 			if (ret < 0) {
738 				return ret;
745 			ret = sca3000_read_data_short(st,
748 			if (ret < 0) {
750 				return ret;
771 		ret = sca3000_read_raw_samp_freq(st, val);
773 		return ret ? ret : IIO_VAL_INT;
776 		ret = sca3000_read_3db_freq(st, val);
778 		return ret;
789 	int ret;
796 		ret = sca3000_write_raw_samp_freq(st, val);
798 		return ret;
803 		ret = sca3000_write_3db_freq(st, val);
805 		return ret;
810 	return ret;
830 	int len = 0, ret, val;
833 	ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
836 	if (ret)
861 	return ret;
881 	long ret;
887 		ret = sca3000_read_ctrl_reg(st,
890 		if (ret < 0)
891 			return ret;
894 			for_each_set_bit(i, &ret,
898 			for_each_set_bit(i, &ret,
933 	int ret;
954 	ret = sca3000_write_ctrl_reg(st,
959 	return ret;
977 	int ret;
989 	ret = spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
990 	if (ret) {
992 		return ret;
1006 	int ret, i, num_available;
1011 		ret = sca3000_read_data_short(st, SCA3000_REG_BUF_COUNT_ADDR,
1013 		if (ret)
1020 		ret = sca3000_read_data(st, SCA3000_REG_RING_OUT_ADDR, st->rx,
1022 		if (ret)
1055 	int ret, val;
1063 	ret = sca3000_read_data_short(st, SCA3000_REG_INT_STATUS_ADDR, 1);
1066 	if (ret)
1120 	int ret;
1124 	ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1125 	if (ret)
1130 		ret = !!(st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT);
1141 			ret = 0;
1143 			ret = sca3000_read_ctrl_reg(st,
1145 			if (ret < 0)
1148 			ret = !!(ret & sca3000_addresses[chan->address][2]);
1152 		ret = -EINVAL;
1158 	return ret;
1164 	int ret;
1167 	ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1168 	if (ret)
1169 		return ret;
1187 	int ret, ctrlval;
1193 	ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL);
1194 	if (ret < 0)
1195 		return ret;
1196 	ctrlval = ret;
1199 		ret = sca3000_write_ctrl_reg(st,
1203 		if (ret)
1204 			return ret;
1207 		ret = sca3000_write_ctrl_reg(st,
1211 		if (ret)
1212 			return ret;
1217 	ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1218 	if (ret)
1219 		return ret;
1259 	int ret;
1264 		ret = sca3000_freefall_set_state(indio_dev, state);
1270 		ret = sca3000_motion_detect_set_state(indio_dev,
1275 		ret = -EINVAL;
1280 	return ret;
1287 	int ret;
1290 	ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1291 	if (ret)
1295 		ret = sca3000_write_reg(st,
1299 		ret = sca3000_write_reg(st,
1305 	return ret;
1319 	int ret;
1325 	ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
1326 	if (ret)
1328 	ret = sca3000_write_reg(st,
1331 	if (ret)
1341 	return ret;
1346 	int ret;
1349 	ret = __sca3000_hw_ring_state_set(indio_dev, 0);
1350 	if (ret)
1351 		return ret;
1356 	ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
1357 	if (ret)
1359 	ret = sca3000_write_reg(st,
1364 	return ret;
1382 	int ret;
1386 	ret = sca3000_read_data_short(st, SCA3000_REG_INT_STATUS_ADDR, 1);
1387 	if (ret)
1391 	ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL);
1392 	if (ret < 0)
1394 	ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL,
1395 				     ret & SCA3000_MD_CTRL_PROT_MASK);
1396 	if (ret)
1400 	ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
1401 	if (ret < 0)
1403 	ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL,
1404 				     (ret & SCA3000_REG_OUT_CTRL_PROT_MASK)
1409 	if (ret)
1412 	ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
1413 	if (ret)
1415 	ret = sca3000_write_reg(st,
1417 				(ret & SCA3000_REG_INT_MASK_PROT_MASK)
1419 	if (ret)
1426 	ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1427 	if (ret)
1429 	ret = sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
1434 	return ret;
1449 	int ret;
1476 	ret = devm_iio_kfifo_buffer_setup(&spi->dev, indio_dev,
1478 	if (ret)
1479 		return ret;
1482 		ret = request_threaded_irq(spi->irq,
1488 		if (ret)
1489 			return ret;
1491 	ret = sca3000_clean_setup(st);
1492 	if (ret)
1495 	ret = sca3000_print_rev(indio_dev);
1496 	if (ret)
1505 	return ret;
1510 	int ret;
1513 	ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
1514 	if (ret)
1516 	ret = sca3000_write_reg(st, SCA3000_REG_INT_MASK_ADDR,
1523 	return ret;