Lines Matching refs:i2c
14 #include <linux/i2c.h>
85 #define I2C_DRV_NAME "i2c-mt65xx"
90 * @I2C_MT65XX_CLK_MAIN: main clock for i2c bus
91 * @I2C_MT65XX_CLK_DMA: DMA clock for i2c via DMA
92 * @I2C_MT65XX_CLK_PMIC: PMIC clock for i2c from PMIC
93 * @I2C_MT65XX_CLK_ARB: Arbitrator clock for i2c
287 struct i2c_adapter adap; /* i2c host adapter */
292 /* set in i2c probe */
293 void __iomem *base; /* i2c base addr */
295 struct clk_bulk_data clocks[I2C_MT65XX_CLK_MAX]; /* clocks for i2c */
296 bool have_pmic; /* can use i2c pins from PMIC */
525 { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat },
526 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
527 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
528 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
529 { .compatible = "mediatek,mt7981-i2c", .data = &mt7981_compat },
530 { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat },
531 { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat },
532 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
533 { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
534 { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat },
535 { .compatible = "mediatek,mt8188-i2c", .data = &mt8188_compat },
536 { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
541 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)
543 return readw(i2c->base + i2c->dev_comp->regs[reg]);
546 static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
549 writew(val, i2c->base + i2c->dev_comp->regs[reg]);
552 static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
558 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_START);
559 intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
560 mtk_i2c_writew(i2c, intr_stat_reg, OFFSET_INTR_STAT);
562 if (i2c->dev_comp->apdma_sync) {
563 writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST);
565 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
568 i2c->pdmabase + OFFSET_RST);
569 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST,
572 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
573 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
575 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
577 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
578 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET);
582 if (i2c->use_push_pull)
583 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG);
585 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG);
587 if (i2c->dev_comp->dcm)
588 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);
590 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
591 mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
592 if (i2c->dev_comp->ltiming_adjust)
593 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);
595 if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ)
600 if (i2c->dev_comp->timing_adjust) {
601 ext_conf_val = i2c->ac_timing.ext;
602 mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div,
604 mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE,
606 mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing,
609 if (i2c->dev_comp->ltiming_adjust) {
610 mtk_i2c_writew(i2c, i2c->ac_timing.htiming,
612 mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS);
613 mtk_i2c_writew(i2c, i2c->ac_timing.ltiming,
616 mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio,
618 mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio,
620 mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop,
622 mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop,
626 mtk_i2c_writew(i2c, ext_conf_val, OFFSET_EXT_CONF);
628 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
629 if (i2c->have_pmic)
630 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR);
634 if (i2c->dev_comp->dma_sync)
637 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
638 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);
659 static int mtk_i2c_get_clk_div_restri(struct mtk_i2c *i2c,
664 if (i2c->dev_comp->ltiming_adjust == 0)
668 if (i2c->ac_timing.inter_clk_div == 0)
673 if (i2c->ac_timing.inter_clk_div == 0)
675 else if (i2c->ac_timing.inter_clk_div == 1)
685 * Check and Calculate i2c ac-timing
696 static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c,
708 if (!i2c->dev_comp->timing_adjust)
711 if (i2c->dev_comp->ltiming_adjust)
716 if (i2c->dev_comp->ltiming_adjust)
722 i2c->timing_info.scl_int_delay_ns, clk_ns);
751 if (i2c->dev_comp->ltiming_adjust) {
752 i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE |
754 i2c->ac_timing.ltiming &= ~GENMASK(15, 9);
755 i2c->ac_timing.ltiming |= (sample_cnt << 12) |
757 i2c->ac_timing.ext &= ~GENMASK(7, 1);
758 i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0);
760 i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) |
762 i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) |
765 i2c->ac_timing.sda_timing &= ~GENMASK(11, 6);
766 i2c->ac_timing.sda_timing |= (1 << 12) |
769 if (i2c->dev_comp->ltiming_adjust) {
770 i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt);
771 i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt);
772 i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0);
774 i2c->ac_timing.scl_hl_ratio = (1 << 12) |
776 i2c->ac_timing.sta_stop = (su_sta_cnt << 8) |
780 i2c->ac_timing.sda_timing = (1 << 12) |
788 * Calculate i2c port speed
795 * less than or equal to i2c->speed_hz. The calculation try to get
798 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,
830 clk_div_restri = mtk_i2c_get_clk_div_restri(i2c, sample_cnt);
837 ret = mtk_i2c_check_ac_timing(i2c, clk_src,
861 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed);
871 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
883 target_speed = i2c->speed_hz;
884 parent_clk /= i2c->clk_src_div;
886 if (i2c->dev_comp->timing_adjust && i2c->dev_comp->ltiming_adjust)
888 else if (i2c->dev_comp->timing_adjust)
895 i2c->ac_timing.inter_clk_div = clk_div - 1;
899 ret = mtk_i2c_calculate_speed(i2c, clk_src,
906 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
909 ret = mtk_i2c_calculate_speed(i2c, clk_src,
915 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
918 if (i2c->dev_comp->ltiming_adjust)
919 i2c->ltiming_reg =
923 ret = mtk_i2c_calculate_speed(i2c, clk_src,
929 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
932 i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
934 if (i2c->dev_comp->ltiming_adjust)
935 i2c->ltiming_reg =
946 static void i2c_dump_register(struct mtk_i2c *i2c)
948 dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n",
949 mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR),
950 mtk_i2c_readw(i2c, OFFSET_INTR_MASK));
951 dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n",
952 mtk_i2c_readw(i2c, OFFSET_INTR_STAT),
953 mtk_i2c_readw(i2c, OFFSET_CONTROL));
954 dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n",
955 mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN),
956 mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN));
957 dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n",
958 mtk_i2c_readw(i2c, OFFSET_DELAY_LEN),
959 mtk_i2c_readw(i2c, OFFSET_TIMING));
960 dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n",
961 mtk_i2c_readw(i2c, OFFSET_START),
962 mtk_i2c_readw(i2c, OFFSET_EXT_CONF));
963 dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n",
964 mtk_i2c_readw(i2c, OFFSET_HS),
965 mtk_i2c_readw(i2c, OFFSET_IO_CONFIG));
966 dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n",
967 mtk_i2c_readw(i2c, OFFSET_DCM_EN),
968 mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX));
969 dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n",
970 mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV),
971 mtk_i2c_readw(i2c, OFFSET_FIFO_STAT));
972 dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n",
973 mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL),
974 mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT));
975 if (i2c->dev_comp->regs == mt_i2c_regs_v2) {
976 dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n",
977 mtk_i2c_readw(i2c, OFFSET_LTIMING),
978 mtk_i2c_readw(i2c, OFFSET_MULTI_DMA));
980 dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n",
981 readl(i2c->pdmabase + OFFSET_INT_FLAG),
982 readl(i2c->pdmabase + OFFSET_INT_EN));
983 dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n",
984 readl(i2c->pdmabase + OFFSET_EN),
985 readl(i2c->pdmabase + OFFSET_CON));
986 dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n",
987 readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR),
988 readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR));
989 dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n",
990 readl(i2c->pdmabase + OFFSET_TX_LEN),
991 readl(i2c->pdmabase + OFFSET_RX_LEN));
992 dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x",
993 readl(i2c->pdmabase + OFFSET_TX_4G_MODE),
994 readl(i2c->pdmabase + OFFSET_RX_4G_MODE));
997 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
1013 i2c->irq_stat = 0;
1015 if (i2c->auto_restart)
1018 reinit_completion(&i2c->msg_complete);
1020 if (i2c->dev_comp->apdma_sync &&
1021 i2c->op != I2C_MASTER_WRRD && num > 1) {
1022 mtk_i2c_writew(i2c, 0x00, OFFSET_DEBUGCTRL);
1024 i2c->pdmabase + OFFSET_RST);
1026 ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST,
1031 dev_err(i2c->dev, "DMA warm reset timeout\n");
1035 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
1036 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET);
1037 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
1038 mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE,
1042 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
1044 if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1))
1047 if (i2c->op == I2C_MASTER_WRRD)
1050 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
1053 mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR);
1056 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
1059 mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR);
1062 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
1066 if (i2c->op == I2C_MASTER_WRRD) {
1067 if (i2c->dev_comp->aux_len_reg) {
1068 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
1069 mtk_i2c_writew(i2c, (msgs + 1)->len,
1072 mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8,
1075 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN);
1077 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
1078 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
1081 if (i2c->dev_comp->apdma_sync) {
1083 if (i2c->op == I2C_MASTER_WRRD)
1088 if (i2c->op == I2C_MASTER_RD) {
1089 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
1090 writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON);
1096 rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
1098 if (dma_mapping_error(i2c->dev, rpaddr)) {
1104 if (i2c->dev_comp->max_dma_support > 32) {
1106 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
1109 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
1110 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
1111 } else if (i2c->op == I2C_MASTER_WR) {
1112 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
1113 writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON);
1119 wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
1121 if (dma_mapping_error(i2c->dev, wpaddr)) {
1127 if (i2c->dev_comp->max_dma_support > 32) {
1129 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
1132 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
1133 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
1135 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
1136 writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON);
1142 wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
1144 if (dma_mapping_error(i2c->dev, wpaddr)) {
1152 dma_unmap_single(i2c->dev, wpaddr,
1160 rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
1163 if (dma_mapping_error(i2c->dev, rpaddr)) {
1164 dma_unmap_single(i2c->dev, wpaddr,
1173 if (i2c->dev_comp->max_dma_support > 32) {
1175 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
1178 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
1181 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
1182 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
1183 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
1184 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
1187 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
1189 if (!i2c->auto_restart) {
1196 mtk_i2c_writew(i2c, start_reg, OFFSET_START);
1198 ret = wait_for_completion_timeout(&i2c->msg_complete,
1199 i2c->adap.timeout);
1202 mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
1205 if (i2c->op == I2C_MASTER_WR) {
1206 dma_unmap_single(i2c->dev, wpaddr,
1210 } else if (i2c->op == I2C_MASTER_RD) {
1211 dma_unmap_single(i2c->dev, rpaddr,
1216 dma_unmap_single(i2c->dev, wpaddr, msgs->len,
1218 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len,
1226 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
1227 i2c_dump_register(i2c);
1228 mtk_i2c_init_hw(i2c);
1232 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
1233 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
1234 mtk_i2c_init_hw(i2c);
1246 struct mtk_i2c *i2c = i2c_get_adapdata(adap);
1248 ret = clk_bulk_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1252 i2c->auto_restart = i2c->dev_comp->auto_restart;
1255 if (i2c->auto_restart && num == 2) {
1258 i2c->auto_restart = 0;
1262 if (i2c->auto_restart && num >= 2 &&
1263 i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)
1267 i2c->ignore_restart_irq = true;
1269 i2c->ignore_restart_irq = false;
1273 dev_dbg(i2c->dev, "data buffer is NULL.\n");
1279 i2c->op = I2C_MASTER_RD;
1281 i2c->op = I2C_MASTER_WR;
1283 if (!i2c->auto_restart) {
1286 i2c->op = I2C_MASTER_WRRD;
1292 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
1302 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1308 struct mtk_i2c *i2c = dev_id;
1312 if (i2c->auto_restart)
1315 intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
1316 mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT);
1319 * when occurs ack error, i2c controller generate two interrupts
1321 * i2c->irq_stat need keep the two interrupt value.
1323 i2c->irq_stat |= intr_stat;
1325 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
1326 i2c->ignore_restart_irq = false;
1327 i2c->irq_stat = 0;
1328 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG |
1331 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
1332 complete(&i2c->msg_complete);
1352 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c)
1356 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
1358 i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ;
1360 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div);
1364 if (i2c->clk_src_div == 0)
1367 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
1368 i2c->use_push_pull =
1371 i2c_parse_fw_timings(i2c->dev, &i2c->timing_info, true);
1379 struct mtk_i2c *i2c;
1382 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
1383 if (!i2c)
1386 i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1387 if (IS_ERR(i2c->base))
1388 return PTR_ERR(i2c->base);
1390 i2c->pdmabase = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
1391 if (IS_ERR(i2c->pdmabase))
1392 return PTR_ERR(i2c->pdmabase);
1398 init_completion(&i2c->msg_complete);
1400 i2c->dev_comp = of_device_get_match_data(&pdev->dev);
1401 i2c->adap.dev.of_node = pdev->dev.of_node;
1402 i2c->dev = &pdev->dev;
1403 i2c->adap.dev.parent = &pdev->dev;
1404 i2c->adap.owner = THIS_MODULE;
1405 i2c->adap.algo = &mtk_i2c_algorithm;
1406 i2c->adap.quirks = i2c->dev_comp->quirks;
1407 i2c->adap.timeout = 2 * HZ;
1408 i2c->adap.retries = 1;
1409 i2c->adap.bus_regulator = devm_regulator_get_optional(&pdev->dev, "vbus");
1410 if (IS_ERR(i2c->adap.bus_regulator)) {
1411 if (PTR_ERR(i2c->adap.bus_regulator) == -ENODEV)
1412 i2c->adap.bus_regulator = NULL;
1414 return PTR_ERR(i2c->adap.bus_regulator);
1417 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c);
1421 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
1426 i2c->clocks[i].id = i2c_mt65xx_clk_ids[i];
1429 i2c->clocks[I2C_MT65XX_CLK_MAIN].clk = devm_clk_get(&pdev->dev, "main");
1430 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk)) {
1432 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk);
1435 i2c->clocks[I2C_MT65XX_CLK_DMA].clk = devm_clk_get(&pdev->dev, "dma");
1436 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk)) {
1438 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk);
1441 i2c->clocks[I2C_MT65XX_CLK_ARB].clk = devm_clk_get_optional(&pdev->dev, "arb");
1442 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk))
1443 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk);
1445 i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get_optional(&pdev->dev, "pmic");
1446 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
1448 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
1451 if (i2c->have_pmic) {
1452 if (!i2c->clocks[I2C_MT65XX_CLK_PMIC].clk) {
1461 strscpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
1463 ret = mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk));
1469 if (i2c->dev_comp->max_dma_support > 32) {
1471 DMA_BIT_MASK(i2c->dev_comp->max_dma_support));
1478 ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1483 mtk_i2c_init_hw(i2c);
1484 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1488 dev_name(&pdev->dev), i2c);
1495 i2c_set_adapdata(&i2c->adap, i2c);
1496 ret = i2c_add_adapter(&i2c->adap);
1500 platform_set_drvdata(pdev, i2c);
1505 clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
1512 struct mtk_i2c *i2c = platform_get_drvdata(pdev);
1514 i2c_del_adapter(&i2c->adap);
1516 clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
1521 struct mtk_i2c *i2c = dev_get_drvdata(dev);
1523 i2c_mark_adapter_suspended(&i2c->adap);
1524 clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
1532 struct mtk_i2c *i2c = dev_get_drvdata(dev);
1534 ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1540 mtk_i2c_init_hw(i2c);
1542 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1544 i2c_mark_adapter_resumed(&i2c->adap);