Lines Matching refs:HVS_WRITE
229 HVS_WRITE(SCALER_GAMADDR,
234 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
236 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
238 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
363 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
364 HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET);
365 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
391 HVS_WRITE(SCALER_DISPCTRLX(chan), dispctrl);
396 HVS_WRITE(SCALER_DISPBKGNDX(chan), dispbkgndx |
421 HVS_WRITE(SCALER_DISPCTRLX(chan),
423 HVS_WRITE(SCALER_DISPCTRLX(chan),
485 HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
629 HVS_WRITE(SCALER_DISPBKGNDX(channel),
658 HVS_WRITE(SCALER_DISPBKGNDX(channel), dispbkgndx);
682 HVS_WRITE(SCALER_DISPCTRL, dispctrl);
700 HVS_WRITE(SCALER_DISPSTAT,
702 HVS_WRITE(SCALER_DISPCTRL, dispctrl);
754 HVS_WRITE(SCALER_DISPSTAT, SCALER_DISPSTAT_IRQMASK(0) |
900 HVS_WRITE(SCALER_DISPECTRL,
905 HVS_WRITE(SCALER_DISPCTRL,
910 HVS_WRITE(SCALER_DISPEOLN,
915 HVS_WRITE(SCALER_DISPDITHER,
965 HVS_WRITE(SCALER_DISPCTRL, dispctrl);
984 HVS_WRITE(SCALER_DISPBASE2, reg);
988 HVS_WRITE(SCALER_DISPBASE1, reg);
992 HVS_WRITE(SCALER_DISPBASE0, reg);
1008 HVS_WRITE(SCALER_DISPBASE2, reg);
1013 HVS_WRITE(SCALER_DISPBASE1, reg);
1018 HVS_WRITE(SCALER_DISPBASE0, reg);