drm/tegra/riscv.c

11 #include "riscv.h"
32 static void riscv_writel(struct tegra_drm_riscv *riscv, u32 value, u32 offset)
34 	writel(value, riscv->regs + offset);
37 int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv)
39 	struct tegra_drm_riscv_descriptor *bl = &riscv->bl_desc;
40 	struct tegra_drm_riscv_descriptor *os = &riscv->os_desc;
41 	const struct device_node *np = riscv->dev->of_node;
47 		dev_err(riscv->dev, "failed to read " name ": %d\n", err); \
62 		dev_err(riscv->dev, "descriptors not available\n");
69 int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address,
76 	riscv_writel(riscv, RISCV_BCR_CTRL_CORE_SELECT_RISCV, RISCV_BCR_CTRL);
79 	riscv_writel(riscv, lower_32_bits(addr >> 8), RISCV_BCR_DMAADDR_PKCPARAM_LO);
80 	riscv_writel(riscv, upper_32_bits(addr >> 8), RISCV_BCR_DMAADDR_PKCPARAM_HI);
83 	riscv_writel(riscv, lower_32_bits(addr >> 8), RISCV_BCR_DMAADDR_FMCCODE_LO);
84 	riscv_writel(riscv, upper_32_bits(addr >> 8), RISCV_BCR_DMAADDR_FMCCODE_HI);
87 	riscv_writel(riscv, lower_32_bits(addr >> 8), RISCV_BCR_DMAADDR_FMCDATA_LO);
88 	riscv_writel(riscv, upper_32_bits(addr >> 8), RISCV_BCR_DMAADDR_FMCDATA_HI);
90 	riscv_writel(riscv, RISCV_BCR_DMACFG_SEC_GSCID(gscid), RISCV_BCR_DMACFG_SEC);
91 	riscv_writel(riscv,
94 	riscv_writel(riscv, RISCV_CPUCTL_STARTCPU_TRUE, RISCV_CPUCTL);
97 		riscv->regs + RISCV_BR_RETCODE, val,
101 		dev_err(riscv->dev, "error during bootrom execution. BR_RETCODE=%d\n", val);