renesas/rcar-du/rcar_du_crtc.c

35 	struct rcar_du_device *rcdu = rcrtc->dev;
37 	return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
42 	struct rcar_du_device *rcdu = rcrtc->dev;
44 	rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
49 	struct rcar_du_device *rcdu = rcrtc->dev;
51 	rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
52 		      rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
57 	struct rcar_du_device *rcdu = rcrtc->dev;
59 	rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
60 		      rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
65 	struct rcar_du_device *rcdu = rcrtc->dev;
68 	rcar_du_write(rcdu, rcrtc->mmio_offset + DSYSR, rcrtc->dsysr);
209 	struct rcar_du_device *rcdu = rcrtc->dev;
215 	if (rcdu->info->dpll_mask & (1 << rcrtc->index)) {
244 	} else if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index) ||
245 		   rcdu->info->dsi_clk_mask & BIT(rcrtc->index)) {
275 	if ((rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs |
276 	     rcdu->info->routes[RCAR_DU_OUTPUT_DPAD1].possible_crtcs |
277 	     rcdu->info->routes[RCAR_DU_OUTPUT_LVDS0].possible_crtcs |
278 	     rcdu->info->routes[RCAR_DU_OUTPUT_LVDS1].possible_crtcs) &
285 	if ((rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs |
286 	     rcdu->info->routes[RCAR_DU_OUTPUT_DPAD1].possible_crtcs) &
343 	struct rcar_du_device *rcdu = rcrtc->dev;
389 	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
390 		if (rcdu->info->gen < 3) {
473 	struct rcar_du_device *rcdu = rcrtc->dev;
480 	dev_warn(rcdu->dev, "page flip timeout\n");
613 	struct rcar_du_device *rcdu = rcrtc->dev;
635 		dev_warn(rcdu->dev, "vertical blanking timeout\n");
726 	struct rcar_du_device *rcdu = rcrtc->dev;
738 	if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index)) {
740 		struct drm_bridge *bridge = rcdu->lvds[rcrtc->index];
751 	if ((rcdu->info->dsi_clk_mask & BIT(rcrtc->index)) &&
754 		struct drm_bridge *bridge = rcdu->dsi[rcrtc->index];
776 	struct rcar_du_device *rcdu = rcrtc->dev;
781 	if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index)) {
783 		struct drm_bridge *bridge = rcdu->lvds[rcrtc->index];
793 	if ((rcdu->info->dsi_clk_mask & BIT(rcrtc->index)) &&
796 		struct drm_bridge *bridge = rcdu->dsi[rcrtc->index];
869 	struct rcar_du_device *rcdu = rcrtc->dev;
874 	if (interlaced && !rcar_du_has(rcdu, RCAR_DU_FEATURE_INTERLACED))
907 	struct rcar_du_device *rcdu = rcrtc->dev;
913 	if (rcdu->info->gen < 3)
1188 	struct rcar_du_device *rcdu = rcrtc->dev;
1212 		if (rcdu->info->gen < 3) {
1234 	struct rcar_du_device *rcdu = rgrp->dev;
1235 	struct platform_device *pdev = to_platform_device(rcdu->dev);
1236 	struct rcar_du_crtc *rcrtc = &rcdu->crtcs[swindex];
1247 	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_CLOCK)) {
1254 	rcrtc->clock = devm_clk_get(rcdu->dev, name);
1256 		dev_err(rcdu->dev, "no clock for DU channel %u\n", hwindex);
1261 	clk = devm_clk_get(rcdu->dev, clk_name);
1266 	} else if (rcdu->info->dpll_mask & BIT(hwindex)) {
1272 		dev_err(rcdu->dev, "can't get dclkin.%u: %d\n", hwindex, ret);
1280 	rcrtc->dev = rcdu;
1286 	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_TVM_SYNC))
1289 	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
1294 	ret = drm_crtc_init_with_planes(&rcdu->ddev, crtc, primary, NULL,
1295 					rcdu->info->gen <= 2 ?
1302 	if (rcdu->cmms[swindex]) {
1303 		rcrtc->cmm = rcdu->cmms[swindex];
1313 	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ)) {
1323 		dev_err(rcdu->dev, "no IRQ for CRTC %u\n", swindex);
1327 	ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
1328 			       dev_name(rcdu->dev), rcrtc);
1330 		dev_err(rcdu->dev,