drm/radeon/radeon_display.c

51 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
57 	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
58 	WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
60 	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
61 	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
62 	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
64 	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
65 	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
66 	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
68 	WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
84 	WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
89 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
95 	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
96 	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
98 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
99 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
100 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
102 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
103 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
104 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
106 	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
107 	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
109 	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
114 		WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
123 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
129 	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
133 	WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
136 	WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
138 	WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
140 	WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
144 	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
146 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
147 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
148 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
150 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
151 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
152 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
154 	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
155 	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
157 	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
162 		WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
168 	WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
173 	WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
176 	WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
179 	WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
180 	       (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
183 	WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
188 		WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
195 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
203 	if (radeon_crtc->crtc_id == 0)
250 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
253 	destroy_workqueue(radeon_crtc->flip_queue);
254 	kfree(radeon_crtc);
284 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
290 	if (radeon_crtc == NULL)
306 	if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
307 		DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
309 				 radeon_crtc->flip_status,
365 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
370 	if (radeon_crtc == NULL)
374 	work = radeon_crtc->flip_work;
375 	if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
376 		DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
378 				 radeon_crtc->flip_status,
385 	radeon_crtc->flip_status = RADEON_FLIP_NONE;
386 	radeon_crtc->flip_work = NULL;
390 		drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);
394 	drm_crtc_vblank_put(&radeon_crtc->base);
396 	queue_work(radeon_crtc->flip_queue, &work->unpin_work);
412 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
414 	struct drm_crtc *crtc = &radeon_crtc->base;
453 	while (radeon_crtc->enabled &&
468 	radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
471 	radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);
473 	radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
487 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
504 	work->crtc_id = radeon_crtc->crtc_id;
548 		base -= radeon_crtc->legacy_display_base_addr;
588 	if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
594 	radeon_crtc->flip_status = RADEON_FLIP_PENDING;
595 	radeon_crtc->flip_work = work;
602 	queue_work(radeon_crtc->flip_queue, &work->flip_work);
684 	struct radeon_crtc *radeon_crtc;
686 	radeon_crtc = kzalloc(sizeof(*radeon_crtc), GFP_KERNEL);
687 	if (radeon_crtc == NULL)
690 	radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);
691 	if (!radeon_crtc->flip_queue) {
692 		kfree(radeon_crtc);
696 	drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
698 	drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
699 	radeon_crtc->crtc_id = index;
700 	rdev->mode_info.crtcs[index] = radeon_crtc;
703 		radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
704 		radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
706 		radeon_crtc->max_cursor_width = CURSOR_WIDTH;
707 		radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
709 	dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
710 	dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
713 		radeon_atombios_init_crtc(dev, radeon_crtc);
715 		radeon_legacy_init_crtc(dev, radeon_crtc);
1686 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1693 	radeon_crtc->h_border = 0;
1694 	radeon_crtc->v_border = 0;
1705 				radeon_crtc->rmx_type = RMX_OFF;
1708 				radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1710 				radeon_crtc->rmx_type = RMX_OFF;
1712 			memcpy(&radeon_crtc->native_mode,
1716 			dst_v = radeon_crtc->native_mode.vdisplay;
1718 			dst_h = radeon_crtc->native_mode.hdisplay;
1728 					radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1730 					radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1732 					radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1734 					radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1735 				radeon_crtc->rmx_type = RMX_FULL;
1737 				dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1739 				dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1743 			if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1755 	if (radeon_crtc->rmx_type != RMX_OFF) {
1759 		radeon_crtc->vsc.full = dfixed_div(a, b);
1762 		radeon_crtc->hsc.full = dfixed_div(a, b);
1764 		radeon_crtc->vsc.full = dfixed_const(1);
1765 		radeon_crtc->hsc.full = dfixed_const(1);