Lines Matching refs:track
46 /* value we track */
117 static void evergreen_cs_track_init(struct evergreen_cs_track *track)
122 track->cb_color_fmask_bo[i] = NULL;
123 track->cb_color_cmask_bo[i] = NULL;
124 track->cb_color_cmask_slice[i] = 0;
125 track->cb_color_fmask_slice[i] = 0;
129 track->cb_color_bo[i] = NULL;
130 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
131 track->cb_color_info[i] = 0;
132 track->cb_color_view[i] = 0xFFFFFFFF;
133 track->cb_color_pitch[i] = 0;
134 track->cb_color_slice[i] = 0xfffffff;
135 track->cb_color_slice_idx[i] = 0;
137 track->cb_target_mask = 0xFFFFFFFF;
138 track->cb_shader_mask = 0xFFFFFFFF;
139 track->cb_dirty = true;
141 track->db_depth_slice = 0xffffffff;
142 track->db_depth_view = 0xFFFFC000;
143 track->db_depth_size = 0xFFFFFFFF;
144 track->db_depth_control = 0xFFFFFFFF;
145 track->db_z_info = 0xFFFFFFFF;
146 track->db_z_read_offset = 0xFFFFFFFF;
147 track->db_z_write_offset = 0xFFFFFFFF;
148 track->db_z_read_bo = NULL;
149 track->db_z_write_bo = NULL;
150 track->db_s_info = 0xFFFFFFFF;
151 track->db_s_read_offset = 0xFFFFFFFF;
152 track->db_s_write_offset = 0xFFFFFFFF;
153 track->db_s_read_bo = NULL;
154 track->db_s_write_bo = NULL;
155 track->db_dirty = true;
156 track->htile_bo = NULL;
157 track->htile_offset = 0xFFFFFFFF;
158 track->htile_surface = 0;
161 track->vgt_strmout_size[i] = 0;
162 track->vgt_strmout_bo[i] = NULL;
163 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
165 track->streamout_dirty = true;
166 track->sx_misc_kill_all_prims = false;
204 struct evergreen_cs_track *track = p->track;
207 palign = MAX(64, track->group_size / surf->bpe);
209 surf->base_align = track->group_size;
226 struct evergreen_cs_track *track = p->track;
229 palign = track->group_size / (8 * surf->bpe * surf->nsamples);
232 surf->base_align = track->group_size;
239 track->group_size, surf->bpe, surf->nsamples);
257 struct evergreen_cs_track *track = p->track;
268 palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
395 struct evergreen_cs_track *track = p->track;
401 mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1;
402 pitch = track->cb_color_pitch[id];
403 slice = track->cb_color_slice[id];
406 surf.mode = G_028C70_ARRAY_MODE(track->cb_color_info[id]);
407 surf.format = G_028C70_FORMAT(track->cb_color_info[id]);
408 surf.tsplit = G_028C74_TILE_SPLIT(track->cb_color_attrib[id]);
409 surf.nbanks = G_028C74_NUM_BANKS(track->cb_color_attrib[id]);
410 surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]);
411 surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]);
412 surf.mtilea = G_028C74_MACRO_TILE_ASPECT(track->cb_color_attrib[id]);
418 id, track->cb_color_info[id]);
430 __func__, __LINE__, id, track->cb_color_pitch[id],
431 track->cb_color_slice[id], track->cb_color_attrib[id],
432 track->cb_color_info[id]);
436 offset = track->cb_color_bo_offset[id] << 8;
444 if (offset > radeon_bo_size(track->cb_color_bo[id])) {
457 bsize = radeon_bo_size(track->cb_color_bo[id]);
458 tmp = track->cb_color_bo_offset[id] << 8;
472 ib[track->cb_color_slice_idx[id]] = slice;
481 track->cb_color_bo_offset[id] << 8, mslice,
482 radeon_bo_size(track->cb_color_bo[id]), slice);
498 struct evergreen_cs_track *track = p->track;
501 if (track->htile_bo == NULL) {
503 __func__, __LINE__, track->db_z_info);
507 if (G_028ABC_LINEAR(track->htile_surface)) {
511 nby = round_up(nby, track->npipes * 8);
517 switch (track->npipes) {
540 __func__, __LINE__, track->npipes);
548 size = roundup(nbx * nby * 4, track->npipes * (2 << 10));
549 size += track->htile_offset;
551 if (size > radeon_bo_size(track->htile_bo)) {
553 __func__, __LINE__, radeon_bo_size(track->htile_bo),
562 struct evergreen_cs_track *track = p->track;
568 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
569 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
570 slice = track->db_depth_slice;
573 surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
574 surf.format = G_028044_FORMAT(track->db_s_info);
575 surf.tsplit = G_028044_TILE_SPLIT(track->db_s_info);
576 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
577 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
578 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
579 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
605 __func__, __LINE__, track->db_depth_size,
606 track->db_depth_slice, track->db_s_info, track->db_z_info);
611 offset = track->db_s_read_offset << 8;
618 if (offset > radeon_bo_size(track->db_s_read_bo)) {
622 (unsigned long)track->db_s_read_offset << 8, mslice,
623 radeon_bo_size(track->db_s_read_bo));
625 __func__, __LINE__, track->db_depth_size,
626 track->db_depth_slice, track->db_s_info, track->db_z_info);
630 offset = track->db_s_write_offset << 8;
637 if (offset > radeon_bo_size(track->db_s_write_bo)) {
641 (unsigned long)track->db_s_write_offset << 8, mslice,
642 radeon_bo_size(track->db_s_write_bo));
647 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
659 struct evergreen_cs_track *track = p->track;
665 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
666 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
667 slice = track->db_depth_slice;
670 surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
671 surf.format = G_028040_FORMAT(track->db_z_info);
672 surf.tsplit = G_028040_TILE_SPLIT(track->db_z_info);
673 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
674 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
675 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
676 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
696 __func__, __LINE__, track->db_depth_size,
697 track->db_depth_slice, track->db_z_info);
704 __func__, __LINE__, track->db_depth_size,
705 track->db_depth_slice, track->db_z_info);
709 offset = track->db_z_read_offset << 8;
716 if (offset > radeon_bo_size(track->db_z_read_bo)) {
720 (unsigned long)track->db_z_read_offset << 8, mslice,
721 radeon_bo_size(track->db_z_read_bo));
725 offset = track->db_z_write_offset << 8;
732 if (offset > radeon_bo_size(track->db_z_write_bo)) {
736 (unsigned long)track->db_z_write_offset << 8, mslice,
737 radeon_bo_size(track->db_z_write_bo));
742 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
933 struct evergreen_cs_track *track = p->track;
939 if (track->streamout_dirty && track->vgt_strmout_config) {
941 if (track->vgt_strmout_config & (1 << i)) {
942 buffer_mask |= (track->vgt_strmout_buffer_config >> (i * 4)) & 0xf;
948 if (track->vgt_strmout_bo[i]) {
949 u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
950 (u64)track->vgt_strmout_size[i];
951 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
954 radeon_bo_size(track->vgt_strmout_bo[i]));
963 track->streamout_dirty = false;
966 if (track->sx_misc_kill_all_prims)
971 if (track->cb_dirty) {
972 tmp = track->cb_target_mask;
974 u32 format = G_028C70_FORMAT(track->cb_color_info[i]);
979 if (track->cb_color_bo[i] == NULL) {
981 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
991 track->cb_dirty = false;
994 if (track->db_dirty) {
996 if (G_028044_FORMAT(track->db_s_info) != V_028044_STENCIL_INVALID &&
997 G_028800_STENCIL_ENABLE(track->db_depth_control)) {
1003 if (G_028040_FORMAT(track->db_z_info) != V_028040_Z_INVALID &&
1004 G_028800_Z_ENABLE(track->db_depth_control)) {
1009 track->db_dirty = false;
1095 struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
1151 track->db_depth_control = radeon_get_ib_value(p, idx);
1152 track->db_dirty = true;
1169 track->db_z_info = radeon_get_ib_value(p, idx);
1178 track->db_z_info &= ~Z_ARRAY_MODE(0xf);
1180 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1187 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1194 track->db_dirty = true;
1197 track->db_s_info = radeon_get_ib_value(p, idx);
1198 track->db_dirty = true;
1201 track->db_depth_view = radeon_get_ib_value(p, idx);
1202 track->db_dirty = true;
1205 track->db_depth_size = radeon_get_ib_value(p, idx);
1206 track->db_dirty = true;
1209 track->db_depth_slice = radeon_get_ib_value(p, idx);
1210 track->db_dirty = true;
1219 track->db_z_read_offset = radeon_get_ib_value(p, idx);
1221 track->db_z_read_bo = reloc->robj;
1222 track->db_dirty = true;
1231 track->db_z_write_offset = radeon_get_ib_value(p, idx);
1233 track->db_z_write_bo = reloc->robj;
1234 track->db_dirty = true;
1243 track->db_s_read_offset = radeon_get_ib_value(p, idx);
1245 track->db_s_read_bo = reloc->robj;
1246 track->db_dirty = true;
1255 track->db_s_write_offset = radeon_get_ib_value(p, idx);
1257 track->db_s_write_bo = reloc->robj;
1258 track->db_dirty = true;
1261 track->vgt_strmout_config = radeon_get_ib_value(p, idx);
1262 track->streamout_dirty = true;
1265 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx);
1266 track->streamout_dirty = true;
1279 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1281 track->vgt_strmout_bo[tmp] = reloc->robj;
1282 track->streamout_dirty = true;
1290 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1291 track->streamout_dirty = true;
1303 track->cb_target_mask = radeon_get_ib_value(p, idx);
1304 track->cb_dirty = true;
1307 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1308 track->cb_dirty = true;
1317 track->nsamples = 1 << tmp;
1326 track->nsamples = 1 << tmp;
1337 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1338 track->cb_dirty = true;
1345 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1346 track->cb_dirty = true;
1357 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1366 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1368 track->cb_dirty = true;
1375 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1384 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1386 track->cb_dirty = true;
1397 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1398 track->cb_dirty = true;
1405 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1406 track->cb_dirty = true;
1417 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1418 track->cb_color_slice_idx[tmp] = idx;
1419 track->cb_dirty = true;
1426 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1427 track->cb_color_slice_idx[tmp] = idx;
1428 track->cb_dirty = true;
1451 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1459 track->cb_color_attrib[tmp] = ib[idx];
1460 track->cb_dirty = true;
1479 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1487 track->cb_color_attrib[tmp] = ib[idx];
1488 track->cb_dirty = true;
1505 track->cb_color_fmask_bo[tmp] = reloc->robj;
1522 track->cb_color_cmask_bo[tmp] = reloc->robj;
1533 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);
1544 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);
1561 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1563 track->cb_color_bo[tmp] = reloc->robj;
1564 track->cb_dirty = true;
1577 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1579 track->cb_color_bo[tmp] = reloc->robj;
1580 track->cb_dirty = true;
1589 track->htile_offset = radeon_get_ib_value(p, idx);
1591 track->htile_bo = reloc->robj;
1592 track->db_dirty = true;
1596 track->htile_surface = radeon_get_ib_value(p, idx);
1599 track->db_dirty = true;
1738 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1757 struct evergreen_cs_track *track = p->track;
1765 if (!(track->reg_safe_bm[i] & m))
1775 struct evergreen_cs_track *track;
1783 track = (struct evergreen_cs_track *)p->track;
2022 track->indirect_draw_buffer_size = radeon_bo_size(reloc->robj);
2044 if (idx_value + size > track->indirect_draw_buffer_size) {
2046 idx_value, size, track->indirect_draw_buffer_size);
2373 TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
2674 struct evergreen_cs_track *track;
2678 if (p->track == NULL) {
2680 track = kzalloc(sizeof(*track), GFP_KERNEL);
2681 if (track == NULL)
2683 evergreen_cs_track_init(track);
2686 track->reg_safe_bm = cayman_reg_safe_bm;
2689 track->reg_safe_bm = evergreen_reg_safe_bm;
2695 track->npipes = 1;
2699 track->npipes = 2;
2702 track->npipes = 4;
2705 track->npipes = 8;
2711 track->nbanks = 4;
2715 track->nbanks = 8;
2718 track->nbanks = 16;
2724 track->group_size = 256;
2728 track->group_size = 512;
2734 track->row_size = 1;
2738 track->row_size = 2;
2741 track->row_size = 4;
2745 p->track = track;
2750 kfree(p->track);
2751 p->track = NULL;
2766 kfree(p->track);
2767 p->track = NULL;
2771 kfree(p->track);
2772 p->track = NULL;
2782 kfree(p->track);
2783 p->track = NULL;