Lines Matching defs:gr
81 gm20b_gr_init_gpc_mmu(struct gf100_gr *gr)
83 struct nvkm_device *device = gr->base.engine.subdev.device;
109 gm20b_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
111 struct nvkm_device *device = gr->base.engine.subdev.device;
141 gm20b_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
143 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
146 ret = nvkm_acr_lsfw_load_bl_inst_data_sig(subdev, &gr->fecs.falcon,
148 "gr/fecs_", ver, fwif->fecs);
153 if (nvkm_firmware_load_blob(subdev, "gr/", "gpccs_inst", ver,
154 &gr->gpccs.inst) ||
155 nvkm_firmware_load_blob(subdev, "gr/", "gpccs_data", ver,
156 &gr->gpccs.data))
159 gr->firmware = true;
161 return gk20a_gr_load_sw(gr, "gr/", ver);
165 MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_bl.bin");
166 MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_inst.bin");
167 MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_data.bin");
168 MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_sig.bin");
169 MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_inst.bin");
170 MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_data.bin");
171 MODULE_FIRMWARE("nvidia/gm20b/gr/sw_ctx.bin");
172 MODULE_FIRMWARE("nvidia/gm20b/gr/sw_nonctx.bin");
173 MODULE_FIRMWARE("nvidia/gm20b/gr/sw_bundle_init.bin");
174 MODULE_FIRMWARE("nvidia/gm20b/gr/sw_method_init.bin");