Lines Matching refs:wr_cio_state
387 wr_cio_state(struct drm_device *dev, int head,
578 wr_cio_state(dev, head, regp, i);
713 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
714 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
715 wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
716 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
717 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
718 wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
719 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
720 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
721 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
724 wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
727 wr_cio_state(dev, head, regp, 0x9f);
729 wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
730 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
731 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
732 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
735 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
737 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
738 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
740 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
741 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
742 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B);
743 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
760 wr_cio_state(dev, head, regp, NV_CIO_CRE_42);
761 wr_cio_state(dev, head, regp, NV_CIO_CRE_53);
762 wr_cio_state(dev, head, regp, NV_CIO_CRE_54);
766 wr_cio_state(dev, head, regp, NV_CIO_CRE_59);
767 wr_cio_state(dev, head, regp, NV_CIO_CRE_5B);
769 wr_cio_state(dev, head, regp, NV_CIO_CRE_85);
770 wr_cio_state(dev, head, regp, NV_CIO_CRE_86);