Lines Matching refs:head
39 NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value)
41 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index);
42 NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value);
46 NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index)
48 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index);
49 return NVReadPRMVIO(dev, head, NV_PRMVIO_SR);
53 NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value)
55 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index);
56 NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value);
60 NVReadVgaGr(struct drm_device *dev, int head, uint8_t index)
62 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index);
63 return NVReadPRMVIO(dev, head, NV_PRMVIO_GX);
66 /* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied)
70 * expected and values can be set for the appropriate head by using a 0x2000
73 * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and
74 * cr44 must be set to 0 or 3 for accessing values on the correct head
76 * b) in tied mode (4) head B is programmed to the values set on head A, and
77 * access using the head B addresses can have strange results, ergo we leave
81 * 0 and 1 are treated as head values and so the set value is (owner * 3)
110 NVBlankScreen(struct drm_device *dev, int head, bool blank)
115 NVSetOwner(dev, head);
117 seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX);
119 NVVgaSeqReset(dev, head, true);
121 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
123 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);
124 NVVgaSeqReset(dev, head, false);
252 nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head)
254 /* the vpll on an unused head can come up with a random value, way
266 enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0;
277 NV_WARN(drm, "VPLL %d outwith limits, attempting to fix\n", head + 1);
380 rd_cio_state(struct drm_device *dev, int head,
383 crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index);
387 wr_cio_state(struct drm_device *dev, int head,
390 NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]);
394 nv_save_state_ramdac(struct drm_device *dev, int head,
398 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
402 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC);
404 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, ®p->pllvals);
409 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11);
411 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL);
414 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630);
416 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634);
418 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP);
419 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL);
420 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW);
421 regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY);
422 regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL);
423 regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW);
424 regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY);
425 regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2);
429 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg);
430 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20);
434 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER);
436 regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4);
437 regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4);
441 regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
442 regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0);
443 if (!nv_gf4_disp_arch(dev) && head == 0) {
445 * the head A FPCLK on (nv11 even locks up) */
449 regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1);
450 regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2);
452 regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR);
455 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0);
458 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20);
459 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24);
460 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34);
463 regp->ctv_regs[i] = NVReadRAMDAC(dev, head,
469 nv_load_state_ramdac(struct drm_device *dev, int head,
474 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
475 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
479 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
486 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither);
488 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl);
491 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630);
493 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634);
495 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup);
496 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal);
497 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew);
498 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay);
499 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal);
500 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew);
501 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay);
502 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2);
507 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]);
508 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]);
512 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither);
514 NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]);
515 NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]);
519 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control);
520 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0);
521 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1);
522 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2);
524 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color);
527 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0);
530 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20);
531 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24);
532 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34);
535 NVWriteRAMDAC(dev, head,
541 nv_save_state_vga(struct drm_device *dev, int head,
544 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
547 regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ);
550 rd_cio_state(dev, head, regp, i);
552 NVSetEnablePalette(dev, head, true);
554 regp->Attribute[i] = NVReadVgaAttr(dev, head, i);
555 NVSetEnablePalette(dev, head, false);
558 regp->Graphics[i] = NVReadVgaGr(dev, head, i);
561 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i);
565 nv_load_state_vga(struct drm_device *dev, int head,
568 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
571 NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg);
574 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]);
576 nv_lock_vga_crtc_base(dev, head, false);
578 wr_cio_state(dev, head, regp, i);
579 nv_lock_vga_crtc_base(dev, head, true);
582 NVWriteVgaGr(dev, head, i, regp->Graphics[i]);
584 NVSetEnablePalette(dev, head, true);
586 NVWriteVgaAttr(dev, head, i, regp->Attribute[i]);
587 NVSetEnablePalette(dev, head, false);
591 nv_save_state_ext(struct drm_device *dev, int head,
595 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
598 rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
599 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
600 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
601 rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
602 rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
603 rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
604 rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
606 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
607 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
608 rd_cio_state(dev, head, regp, NV_CIO_CRE_21);
611 rd_cio_state(dev, head, regp, NV_CIO_CRE_47);
614 rd_cio_state(dev, head, regp, 0x9f);
616 rd_cio_state(dev, head, regp, NV_CIO_CRE_49);
617 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
618 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
619 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
620 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
623 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830);
624 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834);
627 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT);
630 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850);
633 regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL);
634 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG);
637 regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG);
639 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
640 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
642 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
643 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
644 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B);
645 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
649 rd_cio_state(dev, head, regp, NV_CIO_CRE_42);
650 rd_cio_state(dev, head, regp, NV_CIO_CRE_53);
651 rd_cio_state(dev, head, regp, NV_CIO_CRE_54);
654 regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i);
655 rd_cio_state(dev, head, regp, NV_CIO_CRE_59);
656 rd_cio_state(dev, head, regp, NV_CIO_CRE_5B);
658 rd_cio_state(dev, head, regp, NV_CIO_CRE_85);
659 rd_cio_state(dev, head, regp, NV_CIO_CRE_86);
662 regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START);
666 nv_load_state_ext(struct drm_device *dev, int head,
671 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
681 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);
693 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
694 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);
695 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834);
698 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
701 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850);
703 reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900);
705 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000);
707 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000);
711 NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg);
713 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
714 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
715 wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
716 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
717 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
718 wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
719 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
720 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
721 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
724 wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
727 wr_cio_state(dev, head, regp, 0x9f);
729 wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
730 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
731 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
732 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
734 nv_fix_nv40_hw_cursor(dev, head);
735 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
737 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
738 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
740 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
741 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
742 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B);
743 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
760 wr_cio_state(dev, head, regp, NV_CIO_CRE_42);
761 wr_cio_state(dev, head, regp, NV_CIO_CRE_53);
762 wr_cio_state(dev, head, regp, NV_CIO_CRE_54);
765 NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]);
766 wr_cio_state(dev, head, regp, NV_CIO_CRE_59);
767 wr_cio_state(dev, head, regp, NV_CIO_CRE_5B);
769 wr_cio_state(dev, head, regp, NV_CIO_CRE_85);
770 wr_cio_state(dev, head, regp, NV_CIO_CRE_86);
773 NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start);
777 nv_save_state_palette(struct drm_device *dev, int head,
781 int head_offset = head * NV_PRMDIO_SIZE, i;
788 state->crtc_reg[head].DAC[i] = nvif_rd08(device,
792 NVSetEnablePalette(dev, head, false);
796 nouveau_hw_load_state_palette(struct drm_device *dev, int head,
800 int head_offset = head * NV_PRMDIO_SIZE, i;
808 state->crtc_reg[head].DAC[i]);
811 NVSetEnablePalette(dev, head, false);
814 void nouveau_hw_save_state(struct drm_device *dev, int head,
821 nouveau_hw_fix_bad_vpll(dev, head);
822 nv_save_state_ramdac(dev, head, state);
823 nv_save_state_vga(dev, head, state);
824 nv_save_state_palette(dev, head, state);
825 nv_save_state_ext(dev, head, state);
828 void nouveau_hw_load_state(struct drm_device *dev, int head,
831 NVVgaProtect(dev, head, true);
832 nv_load_state_ramdac(dev, head, state);
833 nv_load_state_ext(dev, head, state);
834 nouveau_hw_load_state_palette(dev, head, state);
835 nv_load_state_vga(dev, head, state);
836 NVVgaProtect(dev, head, false);