Lines Matching defs:te
337 struct dpu_hw_tear_check *te)
348 if (te->hw_vsync_mode)
351 cfg |= te->vsync_count;
354 DPU_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_HEIGHT, te->sync_cfg_height);
355 DPU_REG_WRITE(c, INTF_TEAR_VSYNC_INIT_VAL, te->vsync_init_val);
356 DPU_REG_WRITE(c, INTF_TEAR_RD_PTR_IRQ, te->rd_ptr_irq);
357 DPU_REG_WRITE(c, INTF_TEAR_START_POS, te->start_pos);
359 ((te->sync_threshold_continue << 16) |
360 te->sync_threshold_start));
362 (te->start_pos + te->sync_threshold_start + 1));