Lines Matching defs:uncore
22 struct intel_uncore *uncore = gt->uncore;
29 if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 50))
34 intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags);
36 if (IS_GEN9_LP(uncore->i915))
37 intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
39 intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
41 if (GRAPHICS_VER(uncore->i915) == 9) {
43 intel_uncore_rmw(uncore, GEN7_MISCCPCTL, 0,
47 intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF);
52 struct intel_uncore *uncore)
63 intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]);
69 struct intel_uncore *uncore)
73 intel_uncore_write(uncore, UOS_RSA_SCRATCH(0),
81 struct intel_uncore *uncore)
84 return guc_xfer_rsa_vma(guc_fw, uncore);
86 return guc_xfer_rsa_mmio(guc_fw, uncore);
97 static inline bool guc_load_done(struct intel_uncore *uncore, u32 *status, bool *success)
99 u32 val = intel_uncore_read(uncore, GUC_STATUS);
156 struct intel_uncore *uncore = gt->uncore;
190 ret = wait_for(guc_load_done(uncore, &status, &success), 1000);
217 intel_uncore_read(uncore, GUC_HEADER_INFO));
235 intel_uncore_read(uncore, SOFT_SCRATCH(13)));
258 intel_uncore_read(uncore, intel_gt_perf_limit_reasons_reg(gt)));
283 struct intel_uncore *uncore = gt->uncore;
296 ret = guc_xfer_rsa(&guc->fw, uncore);