i915/gt/intel_sseu.c

362 	 * across subslices.
390 	/* BXT has a single slice and at most 3 subslices. */
403 	 * Iterate through enabled slices and subslices to
432 			 * subslices if they are unbalanced.
443 	 * of EU across subslices with the exception that any one
515 	 * Iterate through enabled slices and subslices to
541 			 * Record which subslices have 7 EUs.
552 	 * subslices with the exception that any one EU in any one subslice may
578 	 * There isn't a register to tell us how many slices/subslices. We
662 	u8 slices, subslices;
680 	subslices = hweight8(req_sseu->subslice_mask);
684 	 * wide and Icelake has up to eight subslices, specfial programming is
685 	 * needed in order to correctly enable all subslices.
702 	 * a count of subslices between the SScount maximum of four restriction,
704 	 * subslices are enabled, or a count between one and four on the first
709 	    subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) {
710 		GEM_BUG_ON(subslices & 1);
740 		u32 val = subslices;
793 			drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
870 			seq_printf(m, "  %s Slice%i subslices: %u\n", type,