i915/gt/intel_gt_mcr.c

125 			(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
139 					     intel_uncore_read(gt->uncore,
143 					     intel_uncore_read(gt->uncore, XEHP_FUSE4));
167 			~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
211 	struct intel_uncore *uncore = gt->uncore;
216 	if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 70)) {
224 		intel_uncore_write_fw(uncore, MTL_MCR_SELECTOR,
228 	} else if (GRAPHICS_VER(uncore->i915) >= 11) {
247 		mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
252 		intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
257 		mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
262 		intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
266 		val = intel_uncore_read_fw(uncore, mcr_reg_cast(reg));
268 		intel_uncore_write_fw(uncore, mcr_reg_cast(reg), value);
276 	if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 70) && rw_flag == FW_REG_WRITE)
277 		intel_uncore_write_fw(uncore, MTL_MCR_SELECTOR, GEN11_MCR_MULTICAST);
278 	else if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 70))
279 		intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, old_mcr);
289 	struct intel_uncore *uncore = gt->uncore;
294 	fw_domains = intel_uncore_forcewake_for_reg(uncore, mcr_reg_cast(reg),
296 	fw_domains |= intel_uncore_forcewake_for_reg(uncore,
301 	spin_lock(&uncore->lock);
302 	intel_uncore_forcewake_get__locked(uncore, fw_domains);
306 	intel_uncore_forcewake_put__locked(uncore, fw_domains);
307 	spin_unlock(&uncore->lock);
323  * Context: Takes gt->mcr_lock.  uncore->lock should *not* be held when this
333 	lockdep_assert_not_held(&gt->uncore->lock);
354 		intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_GT);
356 		err = wait_for(intel_uncore_read_fw(gt->uncore,
396 		intel_uncore_write_fw(gt->uncore, MTL_STEER_SEMAPHORE, 0x1);
398 		intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_GT);
421 		intel_uncore_write_fw(gt->uncore, MTL_STEER_SEMAPHORE, 0x1);
484 		intel_uncore_write_fw(gt->uncore, MTL_MCR_SELECTOR, GEN11_MCR_MULTICAST);
486 	intel_uncore_write(gt->uncore, mcr_reg_cast(reg), value);
513 		intel_uncore_write_fw(gt->uncore, MTL_MCR_SELECTOR, GEN11_MCR_MULTICAST);
515 	intel_uncore_write_fw(gt->uncore, mcr_reg_cast(reg), value);
573 		offset += gt->uncore->gsi_offset;
710 	return intel_uncore_read_fw(gt->uncore, mcr_reg_cast(reg));
739 	return intel_uncore_read(gt->uncore, mcr_reg_cast(reg));