Lines Matching defs:gt
141 void intel_gt_mcr_init(struct intel_gt *gt)
143 struct drm_i915_private *i915 = gt->i915;
147 spin_lock_init(>->mcr_lock);
154 gt->info.mslice_mask =
155 intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
157 gt->info.mslice_mask |=
158 (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
161 if (!gt->info.mslice_mask) /* should be impossible! */
162 gt_warn(gt, "mslice mask all zero!\n");
165 if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) {
166 gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
169 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
170 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
172 intel_uncore_read(gt->uncore,
176 intel_uncore_read(gt->uncore, XEHP_FUSE4));
183 gt->info.l3bank_mask |= 0x3 << 2 * i;
185 gt->steering_table[INSTANCE0] = xelpg_instance0_steering_table;
186 gt->steering_table[L3BANK] = xelpg_l3bank_steering_table;
187 gt->steering_table[DSS] = xelpg_dss_steering_table;
189 gt->steering_table[INSTANCE0] = pvc_instance0_steering_table;
191 gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
192 gt->steering_table[LNCF] = dg2_lncf_steering_table;
199 gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
200 gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;
201 gt->steering_table[GAM] = xehpsdv_gam_steering_table;
204 gt->steering_table[L3BANK] = icl_l3bank_steering_table;
205 gt->info.l3bank_mask =
206 ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
208 if (!gt->info.l3bank_mask) /* should be impossible! */
209 gt_warn(gt, "L3 bank mask is all zero!\n");
234 * @gt: GT to read register from
246 static u32 rw_with_mcr_steering_fw(struct intel_gt *gt,
250 struct intel_uncore *uncore = gt->uncore;
253 lockdep_assert_held(>->mcr_lock);
323 static u32 rw_with_mcr_steering(struct intel_gt *gt,
328 struct intel_uncore *uncore = gt->uncore;
339 intel_gt_mcr_lock(gt, &flags);
343 val = rw_with_mcr_steering_fw(gt, reg, rw_flag, group, instance, value);
347 intel_gt_mcr_unlock(gt, flags);
354 * @gt: GT structure
362 * Context: Takes gt->mcr_lock. uncore->lock should *not* be held when this
366 void intel_gt_mcr_lock(struct intel_gt *gt, unsigned long *flags)
367 __acquires(>->mcr_lock)
372 lockdep_assert_not_held(>->uncore->lock);
379 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) {
393 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_GT);
395 err = wait_for(intel_uncore_read_fw(gt->uncore,
405 spin_lock_irqsave(>->mcr_lock, __flags);
415 gt_err_ratelimited(gt, "hardware MCR steering semaphore timed out");
416 add_taint_for_CI(gt->i915, TAINT_WARN); /* CI is now unreliable */
422 * @gt: GT structure
427 * Context: Releases gt->mcr_lock
429 void intel_gt_mcr_unlock(struct intel_gt *gt, unsigned long flags)
430 __releases(>->mcr_lock)
432 spin_unlock_irqrestore(>->mcr_lock, flags);
434 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) {
435 intel_uncore_write_fw(gt->uncore, MTL_STEER_SEMAPHORE, 0x1);
437 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_GT);
443 * @gt: GT structure
451 void intel_gt_mcr_lock_sanitize(struct intel_gt *gt)
457 lockdep_assert_not_held(>->mcr_lock);
459 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
460 intel_uncore_write_fw(gt->uncore, MTL_STEER_SEMAPHORE, 0x1);
465 * @gt: GT structure
470 * Context: Takes and releases gt->mcr_lock
475 u32 intel_gt_mcr_read(struct intel_gt *gt,
479 return rw_with_mcr_steering(gt, reg, FW_REG_READ, group, instance, 0);
484 * @gt: GT structure
493 * Context: Calls a function that takes and releases gt->mcr_lock
495 void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value,
498 rw_with_mcr_steering(gt, reg, FW_REG_WRITE, group, instance, value);
503 * @gt: GT structure
509 * Context: Takes and releases gt->mcr_lock
511 void intel_gt_mcr_multicast_write(struct intel_gt *gt,
516 intel_gt_mcr_lock(gt, &flags);
522 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
523 intel_uncore_write_fw(gt->uncore, MTL_MCR_SELECTOR, GEN11_MCR_MULTICAST);
525 intel_uncore_write(gt->uncore, mcr_reg_cast(reg), value);
527 intel_gt_mcr_unlock(gt, flags);
532 * @gt: GT structure
541 * Context: The caller must hold gt->mcr_lock.
543 void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)
545 lockdep_assert_held(>->mcr_lock);
551 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
552 intel_uncore_write_fw(gt->uncore, MTL_MCR_SELECTOR, GEN11_MCR_MULTICAST);
554 intel_uncore_write_fw(gt->uncore, mcr_reg_cast(reg), value);
559 * @gt: GT structure
573 * Context: Calls functions that take and release gt->mcr_lock
577 u32 intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_mcr_reg_t reg,
580 u32 val = intel_gt_mcr_read_any(gt, reg);
582 intel_gt_mcr_multicast_write(gt, reg, (val & ~clear) | set);
590 * @gt: GT structure
601 static bool reg_needs_read_steering(struct intel_gt *gt,
608 if (likely(!gt->steering_table[type]))
612 offset += gt->uncore->gsi_offset;
614 for (entry = gt->steering_table[type]; entry->end; entry++) {
624 * @gt: GT structure
632 static void get_nonterminated_steering(struct intel_gt *gt,
641 *instance = __ffs(gt->info.l3bank_mask);
644 GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915));
645 *group = __ffs(gt->info.mslice_mask);
653 GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915));
654 *group = __ffs(gt->info.mslice_mask) << 1;
658 *group = IS_DG2(gt->i915) ? 1 : 0;
662 dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0);
675 if ((VDBOX_MASK(gt) | VEBOX_MASK(gt) | gt->info.sfc_mask) & BIT(0))
691 * @gt: GT structure
701 void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt,
708 if (reg_needs_read_steering(gt, reg, type)) {
709 get_nonterminated_steering(gt, type, group, instance);
714 *group = gt->default_steering.groupid;
715 *instance = gt->default_steering.instanceid;
720 * @gt: GT structure
729 * Context: The caller must hold gt->mcr_lock.
733 u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_mcr_reg_t reg)
738 lockdep_assert_held(>->mcr_lock);
741 if (reg_needs_read_steering(gt, reg, type)) {
742 get_nonterminated_steering(gt, type, &group, &instance);
743 return rw_with_mcr_steering_fw(gt, reg,
749 return intel_uncore_read_fw(gt->uncore, mcr_reg_cast(reg));
754 * @gt: GT structure
760 * Context: Calls a function that takes and releases gt->mcr_lock.
764 u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_mcr_reg_t reg)
770 if (reg_needs_read_steering(gt, reg, type)) {
771 get_nonterminated_steering(gt, type, &group, &instance);
772 return rw_with_mcr_steering(gt, reg,
778 return intel_uncore_read(gt->uncore, mcr_reg_cast(reg));
782 struct intel_gt *gt,
791 if (!gt->steering_table[type]) {
797 get_nonterminated_steering(gt, type, &group, &instance);
804 for (entry = gt->steering_table[type]; entry->end; entry++)
808 void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt,
815 if (GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70))
817 gt->default_steering.groupid,
818 gt->default_steering.instanceid);
820 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) {
822 if (gt->steering_table[i])
823 report_steering_type(p, gt, i, dump_table);
824 } else if (IS_PONTEVECCHIO(gt->i915)) {
825 report_steering_type(p, gt, INSTANCE0, dump_table);
826 } else if (HAS_MSLICE_STEERING(gt->i915)) {
827 report_steering_type(p, gt, MSLICE, dump_table);
828 report_steering_type(p, gt, LNCF, dump_table);
834 * @gt: GT structure
842 void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss,
845 if (IS_PONTEVECCHIO(gt->i915)) {
848 } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) {
860 * @gt: GT structure
870 * (intel_gt_mcr_read_any_fw(gt, reg) & mask) == value
885 * Context: Calls a function that takes and releases gt->mcr_lock
888 int intel_gt_mcr_wait_for_reg(struct intel_gt *gt,
897 lockdep_assert_not_held(>->mcr_lock);
899 #define done ((intel_gt_mcr_read_any(gt, reg) & mask) == value)