i915/gt/intel_gt_irq.c

34 	void __iomem * const regs = intel_uncore_regs(gt->uncore);
151 	void __iomem * const regs = intel_uncore_regs(gt->uncore);
186 	void __iomem * const regs = intel_uncore_regs(gt->uncore);
215 	struct intel_uncore *uncore = gt->uncore;
218 	intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0);
219 	intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE,	  0);
221 		intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0);
223 		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0);
226 	intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK,	~0);
227 	intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK,	~0);
229 		intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~0);
231 		intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~0);
233 		intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~0);
235 		intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~0);
236 	intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK,	~0);
237 	intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK,	~0);
239 		intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK,   ~0);
241 		intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK,   ~0);
242 	intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK,	~0);
244 		intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~0);
246 		intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0);
248 		intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0);
250 		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0);
252 	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
253 	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK,  ~0);
254 	intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
255 	intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK,  ~0);
257 	intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, 0);
258 	intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK,  ~0);
263 	struct intel_uncore *uncore = gt->uncore;
293 	intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask);
294 	intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
296 		intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
298 		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, gsc_mask | heci_mask);
301 	intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
302 	intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~smask);
304 		intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
306 		intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
308 		intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
310 		intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
311 	intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~dmask);
312 	intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~dmask);
314 		intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK, ~dmask);
316 		intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK, ~dmask);
317 	intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask);
319 		intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~dmask);
321 		intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask);
323 		intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
325 		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask);
327 		intel_uncore_write(uncore, GEN12_HECI2_RSVD_INTR_MASK,
336 		intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE,
340 		intel_uncore_rmw(uncore, MTL_GUC_MGUC_INTR_MASK, mask, 0);
349 	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
350 	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK,  ~0);
407 	void __iomem * const regs = intel_uncore_regs(gt->uncore);
453 	struct intel_uncore *uncore = gt->uncore;
455 	GEN8_IRQ_RESET_NDX(uncore, GT, 0);
456 	GEN8_IRQ_RESET_NDX(uncore, GT, 1);
457 	GEN8_IRQ_RESET_NDX(uncore, GT, 2);
458 	GEN8_IRQ_RESET_NDX(uncore, GT, 3);
475 	struct intel_uncore *uncore = gt->uncore;
479 	GEN8_IRQ_INIT_NDX(uncore, GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
480 	GEN8_IRQ_INIT_NDX(uncore, GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
485 	GEN8_IRQ_INIT_NDX(uncore, GT, 2, gt->pm_imr, gt->pm_ier);
486 	GEN8_IRQ_INIT_NDX(uncore, GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
499 	intel_uncore_write(gt->uncore, GTIMR, gt->gt_imr);
505 	intel_uncore_posting_read_fw(gt->uncore, GTIMR);
515 	struct intel_uncore *uncore = gt->uncore;
517 	GEN3_IRQ_RESET(uncore, GT);
519 		GEN3_IRQ_RESET(uncore, GEN6_PM);
524 	struct intel_uncore *uncore = gt->uncore;
541 	GEN3_IRQ_INIT(uncore, GT, gt->gt_imr, gt_irqs);
554 		GEN3_IRQ_INIT(uncore, GEN6_PM, gt->pm_imr, pm_irqs);