i915/display/skl_watermark.c

28  * the pipe and planes within 100us. For flip queue use case, the
148  *  - All planes can enable watermarks for latencies >= SAGV engine block time
363 			&crtc_state->wm.skl.optimal.planes[plane_id];
375 		/* Highest common enabled wm level for all planes */
379 	/* No enabled planes? */
385 			&crtc_state->wm.skl.optimal.planes[plane_id];
388 		 * All enabled planes must have enabled a common wm level that
408 			&crtc_state->wm.skl.optimal.planes[plane_id];
1402 	const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
1414 	const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
1431  *  planes must be enabled before the level will be used."
1492 	 * Keep ddb entry of all disabled planes explicitly zeroed
1494 	 * the state when other planes change their allocations.
1519 	/* Clear the partitioning for disabled planes. */
1541 	 * requirement of active planes.
1547 				&crtc_state->wm.skl.optimal.planes[plane_id];
1595 			&crtc_state->wm.skl.optimal.planes[plane_id];
1626 				&crtc_state->wm.skl.optimal.planes[plane_id];
1654 			&crtc_state->wm.skl.optimal.planes[plane_id];
1747 	/* only planar format has two planes */
2107 	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];
2135 	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];
2157 	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
2187 	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
2244 		const struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
2305 				&crtc_state->wm.skl.optimal.planes[plane_id];
2324 				&crtc_state->wm.skl.optimal.planes[plane_id];
2348 		 * planes so for now hack this.
2415 		const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
2450 		const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
2728 			old_wm = &old_pipe_wm->planes[plane_id];
2729 			new_wm = &new_pipe_wm->planes[plane_id];
2840 		const struct skl_plane_wm *old_wm = &old_pipe_wm->planes[plane->id];
2841 		const struct skl_plane_wm *new_wm = &new_pipe_wm->planes[plane->id];
2869  * Other planes do not suffer from this issues as their watermarks are
2871  * can trigger for the other planes is during the initial readout as the
2891 		 * is non-zero, whereas we want all disabled planes to
3013 		struct skl_plane_wm *wm = &out->planes[plane_id];
3107 		/* The slices actually used by the planes on the pipe */
3159 	 * On TGL/RKL (at least) the BIOS likes to assign the planes
3164 	 * the planes (which cannot be allowed or else the hardware
3166 	 * all the planes so that skl_commit_modeset_enables() can
3172 	drm_dbg_kms(&i915->drm, "BIOS has misprogrammed the DBUF, disabling all planes\n");
3238 			hw_wm_level = &hw->wm.planes[plane->id].wm[level];
3255 		hw_wm_level = &hw->wm.planes[plane->id].trans_wm;
3270 		hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0;
3271 		sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0;
3286 		hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm;
3287 		sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm;