i915/display/intel_gmbus.c

51 	struct drm_i915_private *i915;
152 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
158 	if (INTEL_PCH_TYPE(i915) >= PCH_MTL) {
161 	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
164 	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
167 	} else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
170 	} else if (HAS_PCH_CNP(i915)) {
173 	} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
176 	} else if (DISPLAY_VER(i915) == 9) {
179 	} else if (IS_BROADWELL(i915)) {
193 bool intel_gmbus_is_valid_pin(struct drm_i915_private *i915, unsigned int pin)
195 	return get_gmbus_pin(i915, pin);
209 intel_gmbus_reset(struct drm_i915_private *i915)
211 	intel_de_write(i915, GMBUS0(i915), 0);
212 	intel_de_write(i915, GMBUS4(i915), 0);
215 static void pnv_gmbus_clock_gating(struct drm_i915_private *i915,
219 	intel_de_rmw(i915, DSPCLK_GATE_D(i915), PNV_GMBUSUNIT_CLOCK_GATE_DISABLE,
223 static void pch_gmbus_clock_gating(struct drm_i915_private *i915,
226 	intel_de_rmw(i915, SOUTH_DSPCLK_GATE_D, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE,
230 static void bxt_gmbus_clock_gating(struct drm_i915_private *i915,
233 	intel_de_rmw(i915, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS,
239 	struct drm_i915_private *i915 = bus->i915;
243 	if (!IS_I830(i915) && !IS_I845G(i915))
244 		reserved = intel_de_read_notrace(i915, bus->gpio_reg) &
253 	struct drm_i915_private *i915 = bus->i915;
256 	intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
257 	intel_de_write_notrace(i915, bus->gpio_reg, reserved);
259 	return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
265 	struct drm_i915_private *i915 = bus->i915;
268 	intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
269 	intel_de_write_notrace(i915, bus->gpio_reg, reserved);
271 	return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
277 	struct drm_i915_private *i915 = bus->i915;
287 	intel_de_write_notrace(i915, bus->gpio_reg, reserved | clock_bits);
288 	intel_de_posting_read(i915, bus->gpio_reg);
294 	struct drm_i915_private *i915 = bus->i915;
304 	intel_de_write_notrace(i915, bus->gpio_reg, reserved | data_bits);
305 	intel_de_posting_read(i915, bus->gpio_reg);
312 	struct drm_i915_private *i915 = bus->i915;
314 	intel_gmbus_reset(i915);
316 	if (IS_PINEVIEW(i915))
317 		pnv_gmbus_clock_gating(i915, false);
329 	struct drm_i915_private *i915 = bus->i915;
334 	if (IS_PINEVIEW(i915))
335 		pnv_gmbus_clock_gating(i915, true);
358 static bool has_gmbus_irq(struct drm_i915_private *i915)
364 	return HAS_GMBUS_IRQ(i915) && intel_irqs_enabled(i915);
367 static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en)
377 	if (!has_gmbus_irq(i915))
380 	add_wait_queue(&i915->display.gmbus.wait_queue, &wait);
381 	intel_de_write_fw(i915, GMBUS4(i915), irq_en);
384 	ret = wait_for_us((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status,
387 		ret = wait_for((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status,
390 	intel_de_write_fw(i915, GMBUS4(i915), 0);
391 	remove_wait_queue(&i915->display.gmbus.wait_queue, &wait);
400 gmbus_wait_idle(struct drm_i915_private *i915)
408 	if (has_gmbus_irq(i915))
411 	add_wait_queue(&i915->display.gmbus.wait_queue, &wait);
412 	intel_de_write_fw(i915, GMBUS4(i915), irq_enable);
414 	ret = intel_de_wait_fw(i915, GMBUS2(i915), GMBUS_ACTIVE, 0, 10);
416 	intel_de_write_fw(i915, GMBUS4(i915), 0);
417 	remove_wait_queue(&i915->display.gmbus.wait_queue, &wait);
422 static unsigned int gmbus_max_xfer_size(struct drm_i915_private *i915)
424 	return DISPLAY_VER(i915) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
429 gmbus_xfer_read_chunk(struct drm_i915_private *i915,
434 	bool burst_read = len > gmbus_max_xfer_size(i915);
447 		intel_de_write_fw(i915, GMBUS0(i915),
451 	intel_de_write_fw(i915, GMBUS1(i915),
457 		ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
461 		val = intel_de_read_fw(i915, GMBUS3(i915));
472 			intel_de_write_fw(i915, GMBUS0(i915), gmbus0_reg);
489 gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg,
498 		if (HAS_GMBUS_BURST_READ(i915))
501 			len = min(rx_size, gmbus_max_xfer_size(i915));
503 		ret = gmbus_xfer_read_chunk(i915, msg->addr, buf, len,
516 gmbus_xfer_write_chunk(struct drm_i915_private *i915,
529 	intel_de_write_fw(i915, GMBUS3(i915), val);
530 	intel_de_write_fw(i915, GMBUS1(i915),
540 		intel_de_write_fw(i915, GMBUS3(i915), val);
542 		ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
551 gmbus_xfer_write(struct drm_i915_private *i915, struct i2c_msg *msg,
560 		len = min(tx_size, gmbus_max_xfer_size(i915));
562 		ret = gmbus_xfer_write_chunk(i915, msg->addr, buf, len,
589 gmbus_index_xfer(struct drm_i915_private *i915, struct i2c_msg *msgs,
605 		intel_de_write_fw(i915, GMBUS5(i915), gmbus5);
608 		ret = gmbus_xfer_read(i915, &msgs[1], gmbus0_reg,
611 		ret = gmbus_xfer_write(i915, &msgs[1], gmbus1_index);
615 		intel_de_write_fw(i915, GMBUS5(i915), 0);
625 	struct drm_i915_private *i915 = bus->i915;
630 	if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
631 		bxt_gmbus_clock_gating(i915, false);
632 	else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915))
633 		pch_gmbus_clock_gating(i915, false);
636 	intel_de_write_fw(i915, GMBUS0(i915), gmbus0_source | bus->reg0);
641 			ret = gmbus_index_xfer(i915, &msgs[i],
645 			ret = gmbus_xfer_read(i915, &msgs[i],
648 			ret = gmbus_xfer_write(i915, &msgs[i], 0);
652 			ret = gmbus_wait(i915,
664 	intel_de_write_fw(i915, GMBUS1(i915), GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
670 	if (gmbus_wait_idle(i915)) {
671 		drm_dbg_kms(&i915->drm,
676 	intel_de_write_fw(i915, GMBUS0(i915), 0);
695 	if (gmbus_wait_idle(i915)) {
696 		drm_dbg_kms(&i915->drm,
706 	intel_de_write_fw(i915, GMBUS1(i915), GMBUS_SW_CLR_INT);
707 	intel_de_write_fw(i915, GMBUS1(i915), 0);
708 	intel_de_write_fw(i915, GMBUS0(i915), 0);
710 	drm_dbg_kms(&i915->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
721 		drm_dbg_kms(&i915->drm,
730 	drm_dbg_kms(&i915->drm,
733 	intel_de_write_fw(i915, GMBUS0(i915), 0);
743 	if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
744 		bxt_gmbus_clock_gating(i915, true);
745 	else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915))
746 		pch_gmbus_clock_gating(i915, true);
755 	struct drm_i915_private *i915 = bus->i915;
759 	wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS);
771 	intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref);
779 	struct drm_i915_private *i915 = bus->i915;
799 	wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS);
800 	mutex_lock(&i915->display.gmbus.mutex);
809 	mutex_unlock(&i915->display.gmbus.mutex);
810 	intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref);
833 	struct drm_i915_private *i915 = bus->i915;
835 	mutex_lock(&i915->display.gmbus.mutex);
842 	struct drm_i915_private *i915 = bus->i915;
844 	return mutex_trylock(&i915->display.gmbus.mutex);
851 	struct drm_i915_private *i915 = bus->i915;
853 	mutex_unlock(&i915->display.gmbus.mutex);
864  * @i915: i915 device private
866 int intel_gmbus_setup(struct drm_i915_private *i915)
868 	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
872 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
873 		i915->display.gmbus.mmio_base = VLV_DISPLAY_BASE;
874 	else if (!HAS_GMCH(i915))
879 		i915->display.gmbus.mmio_base = PCH_DISPLAY_BASE;
881 	mutex_init(&i915->display.gmbus.mutex);
882 	init_waitqueue_head(&i915->display.gmbus.wait_queue);
884 	for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) {
888 		gmbus_pin = get_gmbus_pin(i915, pin);
901 			 "i915 gmbus %s", gmbus_pin->name);
904 		bus->i915 = i915;
919 		if (IS_I830(i915))
922 		intel_gpio_setup(bus, GPIO(i915, gmbus_pin->gpio));
930 		i915->display.gmbus.bus[pin] = bus;
933 	intel_gmbus_reset(i915);
938 	intel_gmbus_teardown(i915);
943 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *i915,
946 	if (drm_WARN_ON(&i915->drm, pin >= ARRAY_SIZE(i915->display.gmbus.bus) ||
947 			!i915->display.gmbus.bus[pin]))
950 	return &i915->display.gmbus.bus[pin]->adapter;
956 	struct drm_i915_private *i915 = bus->i915;
958 	mutex_lock(&i915->display.gmbus.mutex);
961 	drm_dbg_kms(&i915->drm,
966 	mutex_unlock(&i915->display.gmbus.mutex);
976 void intel_gmbus_teardown(struct drm_i915_private *i915)
980 	for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) {
983 		bus = i915->display.gmbus.bus[pin];
990 		i915->display.gmbus.bus[pin] = NULL;
994 void intel_gmbus_irq_handler(struct drm_i915_private *i915)
996 	wake_up_all(&i915->display.gmbus.wait_queue);