i915/display/intel_dsb.c

48 	 * ins_start_offset will help to store start dword of the dsb
94 static bool assert_dsb_has_room(struct intel_dsb *dsb)
96 	struct intel_crtc *crtc = dsb->crtc;
100 	return !drm_WARN(&i915->drm, dsb->free_pos > dsb->size - 2,
102 			 crtc->base.base.id, crtc->base.name, dsb->id);
105 static void intel_dsb_dump(struct intel_dsb *dsb)
107 	struct intel_crtc *crtc = dsb->crtc;
112 		    crtc->base.base.id, crtc->base.name, dsb->id);
113 	for (i = 0; i < ALIGN(dsb->free_pos, 64 / 4); i += 4)
116 			    intel_dsb_buffer_read(&dsb->dsb_buf, i),
117 			    intel_dsb_buffer_read(&dsb->dsb_buf, i + 1),
118 			    intel_dsb_buffer_read(&dsb->dsb_buf, i + 2),
119 			    intel_dsb_buffer_read(&dsb->dsb_buf, i + 3));
129 static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw)
131 	if (!assert_dsb_has_room(dsb))
135 	dsb->free_pos = ALIGN(dsb->free_pos, 2);
137 	dsb->ins_start_offset = dsb->free_pos;
139 	intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, ldw);
140 	intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, udw);
143 static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb,
153 	if (dsb->free_pos == 0)
156 	prev_opcode = intel_dsb_buffer_read(&dsb->dsb_buf,
157 					    dsb->ins_start_offset + 1) & ~DSB_REG_VALUE_MASK;
158 	prev_reg =  intel_dsb_buffer_read(&dsb->dsb_buf,
159 					  dsb->ins_start_offset + 1) & DSB_REG_VALUE_MASK;
164 static bool intel_dsb_prev_ins_is_mmio_write(struct intel_dsb *dsb, i915_reg_t reg)
167 	return intel_dsb_prev_ins_is_write(dsb,
173 static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_t reg)
175 	return intel_dsb_prev_ins_is_write(dsb,
182  * @dsb: DSB context
189 void intel_dsb_reg_write(struct intel_dsb *dsb,
205 	 * As every instruction is 8 byte aligned the index of dsb instruction
210 	if (!intel_dsb_prev_ins_is_mmio_write(dsb, reg) &&
211 	    !intel_dsb_prev_ins_is_indexed_write(dsb, reg)) {
212 		intel_dsb_emit(dsb, val,
217 		if (!assert_dsb_has_room(dsb))
221 		if (intel_dsb_prev_ins_is_mmio_write(dsb, reg)) {
222 			u32 prev_val = intel_dsb_buffer_read(&dsb->dsb_buf,
223 							     dsb->ins_start_offset + 0);
225 			intel_dsb_buffer_write(&dsb->dsb_buf,
226 					       dsb->ins_start_offset + 0, 1); /* count */
227 			intel_dsb_buffer_write(&dsb->dsb_buf, dsb->ins_start_offset + 1,
230 			intel_dsb_buffer_write(&dsb->dsb_buf, dsb->ins_start_offset + 2, prev_val);
232 			dsb->free_pos++;
235 		intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, val);
237 		old_val = intel_dsb_buffer_read(&dsb->dsb_buf, dsb->ins_start_offset);
238 		intel_dsb_buffer_write(&dsb->dsb_buf, dsb->ins_start_offset, old_val + 1);
241 		if (dsb->free_pos & 0x1)
242 			intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos, 0);
255 void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
258 	intel_dsb_emit(dsb, val,
264 void intel_dsb_noop(struct intel_dsb *dsb, int count)
269 		intel_dsb_emit(dsb, 0,
273 void intel_dsb_nonpost_start(struct intel_dsb *dsb)
275 	struct intel_crtc *crtc = dsb->crtc;
278 	intel_dsb_reg_write_masked(dsb, DSB_CTRL(pipe, dsb->id),
280 	intel_dsb_noop(dsb, 4);
283 void intel_dsb_nonpost_end(struct intel_dsb *dsb)
285 	struct intel_crtc *crtc = dsb->crtc;
288 	intel_dsb_reg_write_masked(dsb, DSB_CTRL(pipe, dsb->id),
290 	intel_dsb_noop(dsb, 4);
293 static void intel_dsb_align_tail(struct intel_dsb *dsb)
297 	tail = dsb->free_pos * 4;
301 		intel_dsb_buffer_memset(&dsb->dsb_buf, dsb->free_pos, 0,
304 	dsb->free_pos = aligned_tail / 4;
307 void intel_dsb_finish(struct intel_dsb *dsb)
309 	struct intel_crtc *crtc = dsb->crtc;
316 	intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(crtc->pipe, dsb->id),
319 	intel_dsb_align_tail(dsb);
321 	intel_dsb_buffer_flush_map(&dsb->dsb_buf);
354 static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
357 	struct intel_crtc *crtc = dsb->crtc;
362 	tail = dsb->free_pos * 4;
366 	if (is_dsb_busy(dev_priv, pipe, dsb->id)) {
368 			crtc->base.base.id, crtc->base.name, dsb->id);
372 	intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id),
375 	intel_de_write_fw(dev_priv, DSB_CHICKEN(pipe, dsb->id),
378 	intel_de_write_fw(dev_priv, DSB_HEAD(pipe, dsb->id),
379 			  intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf));
386 		intel_de_write_fw(dev_priv, DSB_PMCTRL(pipe, dsb->id),
395 		intel_de_write_fw(dev_priv, DSB_PMCTRL_2(pipe, dsb->id),
400 	intel_de_write_fw(dev_priv, DSB_TAIL(pipe, dsb->id),
401 			  intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + tail);
406  * @dsb: DSB context
411 void intel_dsb_commit(struct intel_dsb *dsb,
414 	_intel_dsb_commit(dsb,
416 			  wait_for_vblank ? dsb->dewake_scanline : -1);
419 void intel_dsb_wait(struct intel_dsb *dsb)
421 	struct intel_crtc *crtc = dsb->crtc;
425 	if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) {
426 		u32 offset = intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf);
428 		intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id),
433 			crtc->base.base.id, crtc->base.name, dsb->id,
434 			intel_de_read_fw(dev_priv, DSB_CURRENT_HEAD(pipe, dsb->id)) - offset,
435 			intel_de_read_fw(dev_priv, DSB_HEAD(pipe, dsb->id)) - offset,
436 			intel_de_read_fw(dev_priv, DSB_TAIL(pipe, dsb->id)) - offset);
438 		intel_dsb_dump(dsb);
442 	dsb->free_pos = 0;
443 	dsb->ins_start_offset = 0;
444 	intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id), 0);
452  * This function prepare the command buffer which is used to store dsb
464 	struct intel_dsb *dsb;
474 	dsb = kzalloc(sizeof(*dsb), GFP_KERNEL);
475 	if (!dsb)
483 	if (!intel_dsb_buffer_create(crtc, &dsb->dsb_buf, size))
488 	dsb->id = DSB1;
489 	dsb->crtc = crtc;
490 	dsb->size = size / 4; /* in dwords */
491 	dsb->free_pos = 0;
492 	dsb->ins_start_offset = 0;
493 	dsb->dewake_scanline = intel_dsb_dewake_scanline(crtc_state);
495 	return dsb;
499 	kfree(dsb);
510  * @dsb: DSB context
515 void intel_dsb_cleanup(struct intel_dsb *dsb)
517 	intel_dsb_buffer_cleanup(&dsb->dsb_buf);
518 	kfree(dsb);