Lines Matching refs:smu
150 static int smu_v13_0_4_init_smc_tables(struct smu_context *smu)
152 struct smu_table_context *smu_table = &smu->smu_table;
192 static int smu_v13_0_4_fini_smc_tables(struct smu_context *smu)
194 struct smu_table_context *smu_table = &smu->smu_table;
211 static bool smu_v13_0_4_is_dpm_running(struct smu_context *smu)
216 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
224 static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en)
226 struct amdgpu_device *adev = smu->adev;
234 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
239 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
245 static ssize_t smu_v13_0_4_get_gpu_metrics(struct smu_context *smu,
248 struct smu_table_context *smu_table = &smu->smu_table;
254 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
298 static int smu_v13_0_4_get_smu_metrics_data(struct smu_context *smu,
302 struct smu_table_context *smu_table = &smu->smu_table;
307 ret = smu_cmn_get_metrics_table(smu, NULL, false);
386 static int smu_v13_0_4_get_current_clk_freq(struct smu_context *smu,
406 return smu_cmn_send_smc_msg_with_param(smu,
411 return smu_cmn_send_smc_msg_with_param(smu,
419 return smu_v13_0_4_get_smu_metrics_data(smu, member_type, value);
422 static int smu_v13_0_4_get_dpm_freq_by_index(struct smu_context *smu,
427 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
466 static int smu_v13_0_4_get_dpm_level_count(struct smu_context *smu,
470 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
495 static int smu_v13_0_4_print_clk_levels(struct smu_context *smu,
508 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
510 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
515 smu->gfx_default_hard_min_freq,
516 smu->gfx_default_soft_max_freq);
523 ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value);
527 ret = smu_v13_0_4_get_dpm_level_count(smu, clk_type, &count);
533 ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, idx, &value);
543 ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value);
546 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
547 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
569 static int smu_v13_0_4_read_sensor(struct smu_context *smu,
580 ret = smu_v13_0_4_get_smu_metrics_data(smu,
586 ret = smu_v13_0_4_get_smu_metrics_data(smu,
592 ret = smu_v13_0_4_get_smu_metrics_data(smu,
598 ret = smu_v13_0_4_get_smu_metrics_data(smu,
604 ret = smu_v13_0_4_get_smu_metrics_data(smu,
610 ret = smu_v13_0_4_get_smu_metrics_data(smu,
616 ret = smu_v13_0_4_get_smu_metrics_data(smu,
623 ret = smu_v13_0_4_get_smu_metrics_data(smu,
630 ret = smu_v13_0_4_get_smu_metrics_data(smu,
636 ret = smu_v13_0_4_get_smu_metrics_data(smu,
642 ret = smu_v13_0_4_get_smu_metrics_data(smu,
648 ret = smu_v13_0_4_get_smu_metrics_data(smu,
661 static int smu_v13_0_4_set_watermarks_table(struct smu_context *smu,
666 Watermarks_t *table = smu->smu_table.watermarks_table;
703 smu->watermarks_bitmap |= WATERMARKS_EXIST;
705 /* pass data to smu controller */
706 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
707 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
708 ret = smu_cmn_write_watermarks_table(smu);
710 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
713 smu->watermarks_bitmap |= WATERMARKS_LOADED;
719 static bool smu_v13_0_4_clk_dpm_is_enabled(struct smu_context *smu,
745 return smu_cmn_feature_is_enabled(smu, feature_id);
748 static int smu_v13_0_4_get_dpm_ultimate_freq(struct smu_context *smu,
753 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
758 if (!smu_v13_0_4_clk_dpm_is_enabled(smu, clk_type)) {
762 clock_limit = smu->smu_table.boot_values.uclk;
765 clock_limit = smu->smu_table.boot_values.fclk;
769 clock_limit = smu->smu_table.boot_values.gfxclk;
772 clock_limit = smu->smu_table.boot_values.socclk;
775 clock_limit = smu->smu_table.boot_values.vclk;
778 clock_limit = smu->smu_table.boot_values.dclk;
817 ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type,
848 ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type,
857 static int smu_v13_0_4_set_soft_freq_limited_range(struct smu_context *smu,
867 if (!smu_v13_0_4_clk_dpm_is_enabled(smu, clk_type))
898 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL);
902 return smu_cmn_send_smc_msg_with_param(smu, msg_set_max,
906 static int smu_v13_0_4_force_clk_levels(struct smu_context *smu,
922 ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
926 ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
930 ret = smu_v13_0_4_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
940 static int smu_v13_0_4_get_dpm_profile_freq(struct smu_context *smu,
954 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit);
956 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL);
961 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &clk_limit);
966 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &clk_limit);
968 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, &clk_limit, NULL);
971 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &clk_limit);
974 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &clk_limit);
984 static int smu_v13_0_4_set_performance_level(struct smu_context *smu,
987 struct amdgpu_device *adev = smu->adev;
997 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
998 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max);
999 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max);
1000 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_max);
1001 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max);
1009 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
1010 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL);
1011 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL);
1012 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, NULL);
1013 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, NULL);
1021 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
1022 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max);
1023 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max);
1024 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, &vclk_max);
1025 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max);
1031 smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_SCLK, &sclk_min, &sclk_max);
1032 smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_FCLK, &fclk_min, &fclk_max);
1033 smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_SOCCLK, &socclk_min, &socclk_max);
1034 smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_VCLK, &vclk_min, &vclk_max);
1035 smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max);
1046 ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
1053 smu->gfx_actual_hard_min_freq = sclk_min;
1054 smu->gfx_actual_soft_max_freq = sclk_max;
1058 ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
1067 ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
1076 ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
1085 ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
1095 static int smu_v13_0_4_mode2_reset(struct smu_context *smu)
1097 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
1101 static int smu_v13_0_4_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1103 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1105 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
1106 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
1107 smu->gfx_actual_hard_min_freq = 0;
1108 smu->gfx_actual_soft_max_freq = 0;
1143 static void smu_v13_0_4_set_smu_mailbox_registers(struct smu_context *smu)
1145 struct amdgpu_device *adev = smu->adev;
1147 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
1148 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
1149 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
1152 void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu)
1154 struct amdgpu_device *adev = smu->adev;
1156 smu->ppt_funcs = &smu_v13_0_4_ppt_funcs;
1157 smu->message_map = smu_v13_0_4_message_map;
1158 smu->feature_map = smu_v13_0_4_feature_mask_map;
1159 smu->table_map = smu_v13_0_4_table_map;
1160 smu->smc_driver_if_version = SMU13_0_4_DRIVER_IF_VERSION;
1161 smu->is_apu = true;
1164 smu_v13_0_4_set_smu_mailbox_registers(smu);
1166 smu_v13_0_set_smu_mailbox_registers(smu);